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an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. production data. tps23861 slusbx9e ? march 2014 ? revised march 2016 tps23861 ieee 802.3at quad port power-over-ethernet pse controller 1 1 features 1 ? ieee 802.3at quad port pse controller ? auto detect, classification ? auto turn-on and disconnect ? efficient 255-m sense resistor ? pin-out enables two-layer pcb ? kelvin current sensing ? 4-point detection ? automatic mode ? as shipped ? no external terminal setting required ? no initial i 2 c communication required ? semi-automatic mode ? set by i 2 c command ? continuous identification and classification ? meets ieee 400-ms t pon specification ? fast-port shutdown input ? operates best when used in conjunction with system reference code http://www.ti.com/product/tps23861/toolssoftw are ? optional i 2 c control and monitoring ? ? 40 c to 125 c temperature range ? tssop28 package 9.8 mm x 6.6 mm 2 applications ? ethernet switches and routers ? surveillance nvr and dvrs ? residential gateways ? poe pass-through systems ? wireless backhaul 3 description the tps23861 is an easy-to-use, flexible, ieee802.3at pse solution. as shipped, it automatically manages four 802.3at ports without the need for any external control. the tps23861 automatically detects powered devices (pds) that have a valid signature, determines power requirements according to classification and applies power. two-event classification is supported for type-2 pds. the tps23861 supports dc disconnection and the external fet architecture allows designers to balance size, efficiency and solution cost requirements. the unique pin-out enables 2-layer pcb designs via logical grouping and clear upper and lower differentiation of i 2 c and power pins. this delivers best-in-class thermal performance, kelvin accuracy and low-build cost. in addition to automatic operation, the tps23861 supports semi-auto mode via i 2 c control for precision monitoring and intelligent power management. compliance with the 400-ms t pon specification is ensured whether in semi-automatic or automatic mode. device information order number package body size TPS23861PW tssop (28) 9.80 mm x 6.60 mm simplified schematic reset shtdwn a3 scl sdai ain agnd dgnd ksensx int sdao aout drainn gaten vdd vpwr senn 22 100 nf 100 v 47 255 m note: only port n shown tps23861 portn 48 v 3.3 v top conductors bottom gnd plane continuous, robust backside gnd plane fets uniformly spread over surface productfolder sample &buy technical documents tools & software support &community
2 tps23861 slusbx9e ? march 2014 ? revised march 2016 www.ti.com product folder links: tps23861 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated table of contents 1 features .................................................................. 1 2 applications ........................................................... 1 3 description ............................................................. 1 4 revision history ..................................................... 2 5 pin configuration and functions ......................... 4 6 specifications ......................................................... 5 6.1 absolute maximum ratings ...................................... 5 6.2 esd ratings .............................................................. 5 6.3 recommended operating conditions ....................... 5 6.4 thermal information .................................................. 5 6.5 electrical characteristics ........................................... 6 6.6 timing requirements .............................................. 10 6.7 switching characteristics ........................................ 11 6.8 typical characteristics ............................................ 15 7 detailed description ............................................ 20 7.1 overview ................................................................. 20 7.2 functional block diagram ....................................... 24 7.3 feature description ................................................. 25 7.4 device functional modes ........................................ 41 7.5 register map ? i 2 c-addressable ............................ 47 8 application and implementation ........................ 87 8.1 introduction to poe ................................................. 87 8.2 application information ............................................ 87 8.3 typical application .................................................. 89 8.4 system examples ................................................... 95 9 power supply recommendations ...................... 99 9.1 vdd ......................................................................... 99 9.2 vpwr ..................................................................... 99 9.3 vpwr-reset sequencing .................................... 99 10 layout ................................................................. 100 10.1 layout guidelines ............................................... 100 10.2 layout example .................................................. 101 11 device and documentation support ............... 102 11.1 documentation support ..................................... 102 11.2 community resources ........................................ 102 11.3 trademarks ......................................................... 102 11.4 electrostatic discharge caution .......................... 102 11.5 glossary .............................................................. 102 12 mechanical, packaging, and orderable information ......................................................... 103 4 revision history note: page numbers for previous revisions may differ from page numbers in the current version. changes from revision d (september 2015) to revision e page ? added note in features , " semi-automatic mode " ................................................................................................................. 1 ? aligned format ......................................................................................................................................................................... 1 ? updated pin functions table .................................................................................................................................................. 4 ? added new figure 37 .......................................................................................................................................................... 21 ? added new functional block diagram .................................................................................................................................. 24 ? changed note in a/d converter and i 2 c interface .............................................................................................................. 33 ? changed the note in i 2 c slave address and auto bit programming ................................................................................ 36 ? added note to i 2 c slave address and auto bit programming .......................................................................................... 36 ? changed i 2 c slave address register note. ............................................................................................................................ 36 ? added new figure 43 ........................................................................................................................................................... 40 ? added a note to manual about type 2 power 2 event classification. .................................................................................... 41 ? added content to semi-auto ................................................................................................................................................. 42 ? added " poepn " column to bits description .......................................................................................................................... 72 ? added a note to poe plus register ..................................................................................................................................... 79 changes from revision c (june 2015) to revision d page ? added reference note to figure 5 ........................................................................................................................................ 14 ? added reference note to figure 6 ......................................................................................................................................... 14 ? changed reset note to add addition reference link. ........................................................................................................ 22 ? added sdao pin note. ........................................................................................................................................................ 23 ? changed i 2 c slave address and auto bit programming note. ......................................................................................... 36 ? added figure 42 , i 2 c/smbus interface slave address programming protocol. ................................................................. 39
3 tps23861 www.ti.com slusbx9e ? march 2014 ? revised march 2016 product folder links: tps23861 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated ? added note 3 to table 10 ..................................................................................................................................................... 47 ? changed connections on unused ports section. ................................................................................................................. 88 ? added reference link to the vpwr-reset sequencing note. ............................................................................................ 99 changes from revision b (april 2015) to revision c page ? added figure 5 .................................................................................................................................................................... 14 ? added figure 6 .................................................................................................................................................................... 14 ? changed figure 36 , disconnected ain pin from gnd ......................................................................................................... 21 ? added shtdwn note. ......................................................................................................................................................... 22 ? added reset note. ............................................................................................................................................................ 22 ? added device power on initialization section ...................................................................................................................... 46 ? added note 2 to table 10 ..................................................................................................................................................... 47 ? added port n status register note. ...................................................................................................................................... 57 ? added operating mode register command note. .............................................................................................................. 60 ? added operating mode register bit description note. ........................................................................................................ 60 ? added detect/class enable register command note. ....................................................................................................... 61 ? added detect/class restart register command note. ........................................................................................................ 66 ? added power enable register command note. ................................................................................................................... 67 ? added power enable register bit descriptions note. .......................................................................................................... 67 ? added reset register command note. ................................................................................................................................ 68 ? added reset register bit descriptions note. ...................................................................................................................... 68 ? changed figure 46 , disconnected ain pin from gnd ......................................................................................................... 87 ? changed figure 48 , disconnected ain pin from gnd ......................................................................................................... 89 ? changed figure 49 , disconnected ain pin from gnd ......................................................................................................... 90 ? changed figure 50 , disconnected ain pin from gnd ......................................................................................................... 91 ? changed q pn description in per port components ............................................................................................................. 92 ? changed maximum vdd supply current from 10 ma to 6 ma in first paragraph and changed wording in second paragraph of vdd . ................................................................................................................................................................ 99 ? added vpwr-reset sequencing ...................................................................................................................................... 99 changes from revision a (june, 2014) to revision b page ? changed vdd current consumption from 10 ma (max) to 6.0 ma (max) ............................................................................ 6 ? deleted processor watchdog trip delay specification. .......................................................................................................... 10 ? added when using the i 2 c interface note. .......................................................................................................................... 33 ? added when using the i 2 c interface note. .......................................................................................................................... 36 ? changed full scale value from 146.2 c to 150 c (typical). ....................................................................................... 73 ? changed lsb value from 0.652 c to 7 c. ........................................................................................................................ 73 ? added temperature sensor performance note..................................................................................................................... 73 changes from original (march 2014) to revision a page ? added full tps23861 ieee 802.3at quad port power-over-ethernet pse controller datasheet. ........................................ 1
4 tps23861 slusbx9e ? march 2014 ? revised march 2016 www.ti.com product folder links: tps23861 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated 5 pin configuration and functions pw package 28-pin tssop top view pin functions pin i/o description name no. a3 23 i i 2 c a3 address line. internally pulled up to vdd. agnd 22 p analog ground. ain 25 i i 2 c address programming input line; this pin is internally pulled up to vdd. aout 26 o i 2 c address programming line; this output is open drain. dgnd 7 p digital ground. drain3 9 i port 1-4 output voltage monitor; connect to output port through a 47- resistor. drain4 13 i drain1 16 i drain2 20 i gate3 10 o port 1-4 gate-drive output. gate4 14 o gate1 17 o gate2 21 o int 6 o interrupt; this pin asserts low when a bit in the interrupt register is asserted. this pin is updated between i 2 c transactions. this output is open drain. ksensa 18 i kelvin point connection for sen1 and sen2. ksensb 11 i kelvin point connection for sen3 and sen4. n/c 27 x used to effect regulatory voltage-spacing compliance. leave this pin open. reset 2 i reset; when asserted low, the device resets. this pin is internally pulled up to vdd. scl 3 i serial clock input for i 2 c bus. sdai 4 i serial data input for i 2 c bus; this pin can be connected to sdao for non-isolated systems. sdao 5 o serial data output for i 2 c bus; this pin can be connected to sdai for non-isolated systems. this output is open drain. sen3 8 i port 1-4 current-sense input; connect to current-sense resistor through a 22- resistor. sen4 12 i sen1 15 i sen2 19 i shtdwn 24 i low-priority ports shutdown. vdd 1 p digital 3.3-v supply. bypass vdd to dgnd using a 0.1- f capacitor. vpwr 28 p analog 48-v supply. bypass vpwr to agnd using a 0.1- f capacitor. 12 3 9 4 10 5 11 6 12 7 13 8 14 28 27 26 20 25 19 24 18 23 17 22 16 21 15 vdd reset scl drain3 sdai gate3 sdao ksensb int sen4 dgnd drain4 sen3 gate4 vpwr n/c aout drain2 ain sen2 shtdwn ksensa a3 gate1 agnd drain1 gate2 sen1
5 tps23861 www.ti.com slusbx9e ? march 2014 ? revised march 2016 product folder links: tps23861 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions . exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) do not apply external voltage sources directly. (3) application of voltage is not implied ? these are internally driven pins. (4) if there is a short between drain and gate, the gate pin may internally permanently disconnect to prevent cascade damage. the three other ports will continue to operate. (5) sen1-4 will be tolerant to 15-v transients to avoid fault propagation when a mosfet fails in short-circuit. (6) short transients ( s range) up to 80 v are allowed. 6 specifications 6.1 absolute maximum ratings over operating free-air temperature, voltages are referenced to dgnd and agnd tied together (unless otherwise noted) (1) min max unit input voltage vpwr ? 0.3 70 v input voltage vdd ? 0.3 4 v voltage agnd ? 0.3 0.3 v voltage sdai, sdao (2) , scl, ain, aout, shtdwn, reset, int, a3 (2) ? 0.3 4 v output voltage gate1-4 (3) (4) ? 0.3 13 v input voltage sen1-4 (5) , ksensa, ksensb ? 0.3 3 v voltage drain1-4 (2) (6) ? 0.3 70 v voltage n/c pin 0 70 v sinking current int, sdao 20 ma lead temperature 1.6 mm (1/16-inch) from case for 10 seconds 260 c storage temperature range, t stg ? 65 150 c (1) jedec document jep155 states that 500-v hbm allows safe manufacturing with a standard esd control process. (2) jedec document jep157 states that 250-v cdm allows safe manufacturing with a standard esd control process. 6.2 esd ratings value unit v (esd) electrostatic discharge human-body model (hbm), per ansi/esda/jedec js-001 (1) 2000 v charged-device model (cdm), per jedec specification jesd22- c101 (2) 500 v 6.3 recommended operating conditions over operating free-air temperature, voltages are referenced to dgnd (unless otherwise noted) min nom max unit v vdd 3.0 3.3 3.6 v v vpwr 44 48 57 v voltage slew rate on drain1-4 1 v/ s t j operating junction temperature -40 125 c t a operating free-air temperature -40 85 c (1) for more information about traditional and new thermal metrics, see the ic package thermal metrics application report, spra953 . 6.4 thermal information thermal metric (1) tps23861 unit pw (tssop) 28 pins r ja junction-to-ambient thermal resistance 70.9 c/w r jc(top) junction-to-case (top) thermal resistance 16.2 c/w r jb junction-to-board thermal resistance 28.2 c/w jt junction-to-top characterization parameter 0.6 c/w jb junction-to-board characterization parameter 27.8 c/w
6 tps23861 slusbx9e ? march 2014 ? revised march 2016 www.ti.com product folder links: tps23861 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated (1) these parameters are provided for reference only, and do not constitute part of ti ' s published specifications for purposes of ti ' s product warranty. 6.5 electrical characteristics ? 40 t j +125 c, v vdd = 3.3 v, v vpwr = 48 v, v dgnd = v agnd , dgnd, ksensa and ksensb connected to agnd, and all outputs are unloaded, poepn = 0, positive currents are into pins, r s = 0.255 , to ksensa (sen1 or sen2) or to ksensb (sen3 or sen4), r sens = 22 , r drain = 47 , typical values are at 25 c. all voltages are with respect to agnd, operating registers loaded with default values (unless otherwise noted) parameter test conditions min typ max unit input supply vpwr i vpwr vpwr current consumption v vpwr = 57 v 3.5 7 ma v uvlopw_f vpwr uvlo falling threshold internal oscillator stops operating 14.5 17.5 v v puv_f vpwr undervoltage falling threshold v puv for port de-assertion 25 26.5 28 v v uvlopw_r vpwr uvlo rising threshold 15.5 18.5 v input supply vdd i vdd vdd current consumption 5 6 ma v uvdd_f vdd uvlo falling threshold for port turn off 2 2.2 2.4 v v uvdd_r vdd uvlo rising threshold 2.4 2.6 2.8 v v uvdd_hys hysteresis vdd uvlo (1) 0.4 v detection i det detection current first detection point, v vpwr ? v drainn = 0 v 145 160 190 a 2nd detection point, v vpwr ? v drainn = 0 v 235 270 300 a high current detection point, v vpwr ? v drainn = 0 v 490 540 585 a i det 2nd ? 1st detection currents at v vpwr ? v drainn = 0 v 98 110 118 a v detect open circuit detection voltage v vpwr ? v drainn 17.5 19 22 v r rej_low rejected resistance low range 0.85 15 k ? r rej_hi rejected resistance high range 33 50 k ? r accept accepted resistance range 19 25 26.5 k ? r short shorted port threshold 350 r open open port threshold 55 k ? classification v class classification voltage v vpwr ? v drainn , v senn 0 mv , i port 180 a, 15.5 18.5 20.5 v i class_lim classification current limit v vpwr ? v drainn = 0 v 70 90 ma i class_th classification threshold current class 0-1 5 8 ma class 1-2 13 16 ma class 2-3 21 25 ma class 3-4 31 35 ma class 4- overcurrent 45 51 ma v mark mark voltage 4 ma i port 180 a, v vpwr ? v drainn 7 10 v i mark_lim mark sinking current limit v vpwr ? v drainn = 0 v 10 70 90 ma
7 tps23861 www.ti.com slusbx9e ? march 2014 ? revised march 2016 product folder links: tps23861 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated electrical characteristics (continued) ? 40 t j +125 c, v vdd = 3.3 v, v vpwr = 48 v, v dgnd = v agnd , dgnd, ksensa and ksensb connected to agnd, and all outputs are unloaded, poepn = 0, positive currents are into pins, r s = 0.255 , to ksensa (sen1 or sen2) or to ksensb (sen3 or sen4), r sens = 22 , r drain = 47 , typical values are at 25 c. all voltages are with respect to agnd, operating registers loaded with default values (unless otherwise noted) parameter test conditions min typ max unit gate v goh gate drive voltage v gaten , i gate = ? 1 a 10 12.5 v i go- gate sinking current with power-on reset, shutdown detected or port turn off command v gaten = 5 v 80 100 150 ma i go short ? gate sinking current with port short- circuit v gaten = 5 v, v senn v short (or v short2x if 2x mode) 80 100 150 ma i go+ gate sourcing current v gaten = 0 v, igate = 0 39 50 63 a igate = 1 18 25 34 a drain input v pgt power good threshold measured at v drainn 1.0 2.13 3 v v sht shorted fet threshold measured at v drainn 4 6 8 v r drain resistance from drainn to vpwr any operating mode except during detection or while the port is on, including in device reset state 80 100 190 k ? i drain drainn pin bias current v drainn = 48 v, port off (not in detection) 1 a v vpwr - v drainn = 30 v, port on 75 100 a a/d converter t conv conversion time , a/d #1 to 4 all ranges, each port current 0.65 0.8 1 ms a dcbw (1) adc integration bandwidth ( ? 3 db) (1) 320 hz t int_cur integration (averaging) time, current each port, port on current 80 100 125 ms t int_det integration (averaging) time, detection (1) mains bit = 0 20 ms powered port voltage conversion scale factor and accuracy at v vpwr ? v drainn = 57 v, 0 c to 125 c 15175 15565 15955 counts at v vpwr ? v drainn = 44 v, 0 c to 125 c 11713 12015 12316 counts at v vpwr ? v drainn = 57 v, ? 40 c to 125 c 15020 15565 16110 counts at v vpwr ? v drainn = 44 v, ? 40 c to 125 c 11594 12015 12436 counts powered port current conversion scale factor and accuracy at port current = 770 ma 12300 12616 12932 counts at port current = 7.5 ma 90 123 156 counts input voltage conversion scale factor and accuracy at v vpwr = 57 v 15175 15565 15955 counts at v vpwr = 44 v 11713 12015 12316 counts v os powered port voltage conversion offset at v vpwr ? v drainn = 0.3 v 0 600 mv v /v port voltage reading accuracy at 44 v to 57 v ? 40 c to 125 c ? 3.5% 3.5% at 44 v to 57 v 0 c to 125 c ? 2.5% 2.5% i /i port current reading accuracy at 50 ma to 770 ma ? 2.5% 2.5%
8 tps23861 slusbx9e ? march 2014 ? revised march 2016 www.ti.com product folder links: tps23861 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated electrical characteristics (continued) ? 40 t j +125 c, v vdd = 3.3 v, v vpwr = 48 v, v dgnd = v agnd , dgnd, ksensa and ksensb connected to agnd, and all outputs are unloaded, poepn = 0, positive currents are into pins, r s = 0.255 , to ksensa (sen1 or sen2) or to ksensb (sen3 or sen4), r sens = 22 , r drain = 47 , typical values are at 25 c. all voltages are with respect to agnd, operating registers loaded with default values (unless otherwise noted) parameter test conditions min typ max unit port current sense v cut i cut limit v drainn = 0 v, i cut port n[2:0] = 000, default 90.60 95.37 100.14 mv v drainn = 0 v, i cut port n[2:0] = 001 26.65 28.05 29.45 mv v drainn = 0 v, i cut port n[2:0] = 010 49.42 52.02 54.62 mv v drainn = 0 v, i cut port n[2:0] = 110 156.27 164.5 172.72 mv v drainn = 0 v, i cut port n[2:0] = 111 222.87 234.6 246.33 mv icut /i cut i cut tolerance ? 5% 5% v inrush i inrush limit at port turn on, v vpwr ? v drainn = 1 v 10 23 31 mv v vpwr - v drainn = 10 v 20 33 46 mv v vpwr - v drainn = 30 v 102 114.7 mv v vpwr ? v drainn = 55 v 102 114.7 mv v lim ilim limit with poepn = 0 v drainn = 1 v 102 114.7 mv v drainn = 13 v 102 114.7 mv v drainn = 30 v 15 23 31 mv v drainn = 48 v 15 23 31 mv v lim2x ilim limit with poepn = 1 v drainn = 1 v 260 270.3 285 mv v drainn = 10 v 127 140 153 mv v drainn = 30 v 15 23 31 mv v drainn = 48 v 15 23 31 mv v short i short threshold with poepn = 0 threshold for gate to be less than 1 v, 2 s after application of pulse 140 183 mv v short2x i short threshold with poepn = 1 357 408 mv i bias sense pin bias current port on or during class -2.25 0 a v i(min) disconnect threshold dcthn = 00, default 1.275 2.55 mv dcthn = 01 2.55 5.1 mv dcthn = 10 5.1 10.2 mv dcthn = 11 8.5 17 mv
9 tps23861 www.ti.com slusbx9e ? march 2014 ? revised march 2016 product folder links: tps23861 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated electrical characteristics (continued) ? 40 t j +125 c, v vdd = 3.3 v, v vpwr = 48 v, v dgnd = v agnd , dgnd, ksensa and ksensb connected to agnd, and all outputs are unloaded, poepn = 0, positive currents are into pins, r s = 0.255 , to ksensa (sen1 or sen2) or to ksensb (sen3 or sen4), r sens = 22 , r drain = 47 , typical values are at 25 c. all voltages are with respect to agnd, operating registers loaded with default values (unless otherwise noted) parameter test conditions min typ max unit digital interface at v vdd = 3.3 v v ih digital input high 2.1 v v il digital input low 0.9 v v it_hys input voltage hysteresis (scl, sdai, ain, a3, reset, shtdwn) 0.17 v v ol digital output low, sdao i ol = 9 ma 0.4 v digital output low, int i ol = 3 ma 0.4 v r pullup pullup resistor to vdd reset, ain, a3, shtdwn 30 50 80 k ? aout output v ol_aout aout output low voltage during slave address programming, i aout = 1 ma 0.7 v eeprom (i 2 c slave address) n ee_cyc eeprom endurance 40 v < v vpwr < 57 v 25 cycles t wc write cycle time (byte or page) 40 v < v vpwr < 57 v 10 100 ms thermal shutdown t sd thermal shutdown temperature temperature rising 143 154 161 c hysteresis (1) 8 c
10 tps23861 slusbx9e ? march 2014 ? revised march 2016 www.ti.com product folder links: tps23861 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated (1) these parameters are provided for reference only, and do not constitute part of ti ' s published specifications for purposes of ti ' s product warranty. 6.6 timing requirements ? 40 t j +125 c, v vdd = 3.3 v, v vpwr = 48 v, v dgnd = v agnd , dgnd, ksensa and ksensb connected to agnd, and all outputs are unloaded, poepn = 0, positive currents are into pins, r s = 0.255 , to ksensa (sen1 or sen2) or to ksensb (sen3 or sen4), r sens = 22 , r drain = 47 , typical values are at 25 c. all voltages are with respect to agnd, operating registers loaded with default values (unless otherwise noted) min typ max unit f scl scl clock frequency 10 400 khz t low low period of scl clock 1.3 s t high high period of scl clock 0.6 s t fo sdao output fall time, sdao, 2.3 0.8 v, c b = 10 pf, 10-k pullup to 3.3 v 21 250 ns sdao output fall time, sdao, 2.3 0.8 v, c b = 400 pf, 1.3-k pullup to 3.3 v 60 250 ns c i2c scl capacitance 10 pf c i2c_sda sdai, sdao capacitance 6 pf t su,datw data set-up time (write operation) 100 ns t su,datr data set-up time (read operation), sdao, 2.3 ? 0.8 v, c b = 400 pf, 1.3-k pull up to 3.3 v 600 ns t hd,datw data hold time (write operation) 0 ns t hd,datr data hold time (read operation) 150 600 ns t fsda input fall times of sdai, 2.3 0.8 v 20 250 ns t rsda input rise times of sdai, 0.8 2.3 v 20 300 ns t r input rise time of scl, 0.8 2.3 v 20 300 ns t f input fall time of scl, 2.3 0.8 v 20 200 ns t buf bus free time between a stop and start condition 1.3 s t hd,sta hold time after (repeated) start condition 0.6 s t su,sta repeated start condition set-up time 0.6 s t su,sto stop condition set-up time 0.6 s t flt_ int (1) fault to int assertion, time to internally register an interrupt in response to a fault 150 s t ara_ int ara to int negation 500 ns t dg suppressed spike pulse width, sdai and scl 50 ns t rdg reset input minimum pulse width (deglitch time) 5 s t wdt_i2c i 2 c watchdog trip delay 1.1 2.2 3.3 s t stp_aout delay stop bit to a out high during i 2 c address programming 1.25 s figure 1. i 2 c timings t fsda t fo repeated start condition t low t su,dat t hd,dat scl sdai/ sdao t r t f t rsda t high start condition stop condition start condition t su,sto t hd,sta t su,sta t buf
11 tps23861 www.ti.com slusbx9e ? march 2014 ? revised march 2016 product folder links: tps23861 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated 6.7 switching characteristics ? 40 t j +125 c, v vdd = 3.3 v, v vpwr = 48 v, v dgnd = v agnd , dgnd, ksensa and ksensb connected to agnd, and all outputs are unloaded, poepn = 0, positive currents are into pins, r s = 0.255 , to ksensa (sen1 or sen2) or to ksensb (sen3 or sen4), r sens = 22 , r drain = 47 , typical values are at 25 c. all voltages are with respect to agnd, operating registers loaded with default values (unless otherwise noted) parameter test conditions min typ max unit ifault duty cycle of i port with current fault 5.5% 6.7% t ovld i cut time limit ticut = 00, default as supplied 50 70 ms ticut = 01 25 35 ms ticut = 10 100 140 ms ticut = 11 200 280 ms t lim ilim time limit poepn = 0, default as supplied 50 70 ms poepn = 1, tlim = 00 50 70 ms poepn = 1, tlim = 01 28.4 30 34 ms poepn = 1, tlim = 10 14.7 15.5 17 ms poepn = 1, tlim = 11 9.025 11.5 ms t start maximum current limit duration in port start-up tstart = 00, default as supplied 50 70 ms tstart = 01 25 35 ms tstart = 10 100 140 ms t det four-point detection duration time to complete a detection 275 500 ms t det_boff pause between detection attempts v vpwr ? v drainn > 2.5 v 300 400 500 ms v vpwr ? v drainn < 2.5 v 0 150 ms t cle classification duration 1st and 2nd class event, auto mode, semi-auto mode, from detection complete 6.5 13 ms t pdc classification duration 1-event physical layer class timing, auto mode and semi-auto mode, from detection complete 6.5 13 ms manual mode, from beginning of classification 6.5 14 ms t me mark duration 1st and 2nd mark event, from class 4 complete 6 12 ms t p(on) port power-on delay manual mode, from port turn-on command to port turn on completed 4 ms
12 tps23861 slusbx9e ? march 2014 ? revised march 2016 www.ti.com product folder links: tps23861 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated switching characteristics (continued) ? 40 t j +125 c, v vdd = 3.3 v, v vpwr = 48 v, v dgnd = v agnd , dgnd, ksensa and ksensb connected to agnd, and all outputs are unloaded, poepn = 0, positive currents are into pins, r s = 0.255 , to ksensa (sen1 or sen2) or to ksensb (sen3 or sen4), r sens = 22 , r drain = 47 , typical values are at 25 c. all voltages are with respect to agnd, operating registers loaded with default values (unless otherwise noted) parameter test conditions min typ max unit t ed fault delay timing. delay before next attempt to power a port following power removal due to fault condition icut , ilim or start fault, auto mode, semi-auto mode, cldn = 0x, default as supplied 0.8 1 1.2 s icut , ilim or start fault, auto mode, semi-auto mode, cldn = 10 1.6 2 2.4 s icut , ilim or start fault, auto mode, semi-auto mode, cldn = 11 3.2 4 4.8 s t mpdo pd maintain power signature dropout time limit tdis = 00, default as supplied 300 400 ms tdis = 01 75 100 ms tdis = 10 150 200 ms tdis = 11 600 800 ms t d_off_ shdw n gate turn-off time from shtdwn input from shtdwn to v gaten < 1 v, v senn = 0 v 1 5 s t p_off_cmd gate turn-off time from port off command from port off command to v gaten < 1 v, v senn = 0 v 900 s t p_off_rst gate turn-off time with reset pin from reset low to, v gaten < 1 v, v senn = 0 v 1 5 s t d_off_sen gate turn-off time from senn input poepn = 0, v drainn = 1 v , from v senn pulsed to 0.425 v 0.9 s poepn = 1, v drainn = 1 v , from v senn pulsed to 0.62 v 0.9 s t por device power-on-reset delay 23 ms t reset reset time duration from reset pin 1 5 s figure 2. overcurrent fault timing sen gate 0v 0v v lim v cut t ovld
13 tps23861 www.ti.com slusbx9e ? march 2014 ? revised march 2016 product folder links: tps23861 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated figure 3. detection, 1-event classification, and turn on figure 4. detection, 2-event classification, and turn on t pon v port 0 v four-point detection t det t cle t me class v class v mark mark port turn-on four-point detection class port turn-on t det t pdc v port 0 v v class
14 tps23861 slusbx9e ? march 2014 ? revised march 2016 www.ti.com product folder links: tps23861 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated figure 5. vdd power-on-reset (for more information refer to the application note, tps23861 power-on considerations, slva723 .) figure 6. vpwr power-on-reset (for more information refer to the application note, tps23861 power-on considerations, slva723 .) time v vpwr v uvlopw_ r t por 44v < v vpwr < 57v v uvlopw _ f time v vdd v uvddr t por 0v < v vdd < 3.6v v uvddf 3.
15 tps23861 www.ti.com slusbx9e ? march 2014 ? revised march 2016 product folder links: tps23861 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated 6.8 typical characteristics figure 7. vdd uvlo vs junction temperature figure 8. vpwr uvlo vs junction temperature figure 9. dc disconnect vs junction temperature figure 10. vdd current vs vdd figure 11. vpwr current vs vpwr figure 12. current limit (1x threshold) vs junction temperature 4.00 4.50 5.00 5.50 6.00 6.50 7.00 20.00 30.00 40.00 50.00 60.00 i vpwr vpwr current-ma vpwr-v tj=25c tj=125c tj=-40c c005 105 106 107 108 109 110 40 20 0 20 40 60 80 100 120 v lim -current limit-mv t j -junction temperature- c c006 1.5 1.6 1.7 1.8 1.9 2.0 40.0 20.0 0.0 20.0 40.0 60.0 80.0 100.0 120.0 vimn-dc disconnect-mv t j -junction temperature- ? c c003 5.0 5.5 6.0 6.5 7.0 2.70 2.80 2.90 3.00 3.10 3.20 3.30 3.40 3.50 3.60 3.70 i vdd -vdd current-ma v dd -v tj=-40c tj=25c tj=125c c004 14.0 14.5 15.0 15.5 16.0 16.5 17.0 40.0 20.0 0.0 20.0 40.0 60.0 80.0 100.0 120.0 v uvlopwr_f -vpwr uvlo-v t j -junction temperature- ? c c002 2.0 2.1 2.2 2.3 2.4 40 20 0 20 40 60 80 100 120 v uvdd -vdd uvlo-v t j -junction temperature- ? c c001
16 tps23861 slusbx9e ? march 2014 ? revised march 2016 www.ti.com product folder links: tps23861 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated typical characteristics (continued) figure 13. inrush current limit threshold vs port voltage figure 14. current limit threshold vs fet voltage figure 15. current limit (2x threshold) vs junction temperature figure 16. classification voltage vs port classification current figure 17. valid pd detection (25 k ? and 0.1 f) and class 0 classification figure 18. valid pd detection (25 k ? and 0.1 f) and class 3 classification 270 272 274 276 278 280 40 20 0 20 40 60 80 100 120 v limt2x -current limit-mv t j -junction temperature- c c009 12 14 16 18 20 22 0 10 20 30 40 50 60 70 v class -classification voltage-v classification current-ma tj=-40c tj=25c tj=125c c010 0 10 20 30 40 50 60 70 80 90 100 110 120 0 10 20 30 40 50 v inrush -inrush limit threshold-mv port voltage-v c007 0 50 100 150 200 250 300 0 10 20 30 40 50 i lim -limit-mv fet v ds -v 1x 2x c008
17 tps23861 www.ti.com slusbx9e ? march 2014 ? revised march 2016 product folder links: tps23861 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated typical characteristics (continued) figure 19. detection with invalid pd (15 k and 0.1 f) figure 20. detection with invalid pd (open circuit) figure 21. detection with invalid pd (25 k and 10 f) figure 22. 2-event class and startup with valid pd figure 23. powering up into a 100- f load figure 24. semi-auto sequenced turn on
18 tps23861 slusbx9e ? march 2014 ? revised march 2016 www.ti.com product folder links: tps23861 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated typical characteristics (continued) figure 25. all ports fast shutdown figure 26. overcurrent (i cut ) timeout figure 27. rapid response to a 1- short: 802.3af mode figure 28. rapid response to a 1- short: poe+ mode figure 29. response to a 50- load: 802.3af mode figure 30. response to a 25- load: poe+ mode
19 tps23861 www.ti.com slusbx9e ? march 2014 ? revised march 2016 product folder links: tps23861 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated typical characteristics (continued) figure 31. current limit timeout: 802.3af mode, 85- load figure 32. current limit 15-ms timeout: poe+ mode, 45- load figure 33. inrush fault timeout: 100- load figure 34. current limit timeout restart delay figure 35. response to 8-ma to 6-ma load, dc disconnect enabled
20 tps23861 slusbx9e ? march 2014 ? revised march 2016 www.ti.com product folder links: tps23861 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated 7 detailed description 7.1 overview the tps23861 is a four-port pse for power over ethernet applications. each of the four ports provides fully automatic detection, classification, protection, and shut down in compliance with the ieee 802.3at standard. the schematic of figure 36 depicts automatic mode operation of the tps23861, providing turnkey functionality ready to power poe loads. no connection to the i 2 c bus or any type of host control is required. in figure 36 the tps23861 automatically: 1. performs four-point load detection. 2. performs classification including type-2 (two-finger) of up to class 4 loads. 3. enables power with protective foldback current limiting, and icut value based on load class. 4. shuts down in the event of fault loads and shorts. 5. performs maintain power signature function to ensure removal of power if load is disconnected. 6. undervoltage lock out occurs if vpwr falls below v puv_f (typical 26.5 v). following a power-off command, disconnect or shutdown due to a start, icut or ilim fault, the port powers down. following port power off due to a power off command or disconnect, the tps23861 will continue automatic operation starting with a detection cycle. if the shutdown is due to a start, icut or ilim fault, the tps23861 enters into a cool-down period. after the end of the cool-down period the tps23861 continues automatic operation starting with a detection cycle. the tps23861 will not automatically apply power to a port under the following circumstances: ? the detect status is not resistance valid. ? if the classification status is overcurrent, class mismatch, or unknown.
21 tps23861 www.ti.com slusbx9e ? march 2014 ? revised march 2016 product folder links: tps23861 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated overview (continued) figure 36. automatic 4-port operation schematic figure 37. simplified block diagram copyright ? 2016, texas instruments incorporated port 2 4 analog control functions port 1 analog control functions idet = 160/270/ 540 a gm driver foldback schedulers fast ishort protection dv/dt ramping control rapid overload recovery gatex senx ilim processor class current limit class port voltage control vdd vpwr drainx ksensea,b 0.255 pd load vpwr reset shtdwn 14 13 12 11 10 9 8 7 6 5 4 3 2 1 vdd scl sdai sdao dgnd sen3 drain3 gate3 ksensb sen4 drain4 gate4 15 16 17 18 19 20 21 22 23 24 25 26 27 28 vpwr n/c aout ain shtdwn a3 agnd gate2 drain2 sen2 ksensa gate1 drain1 sen1 reset int 22.1 : : 0.1 p f 50v 0.1 p f 100v : : : 22.1 : 22.1 : 22.1 : smbj58a-13-f 0.1 p f 100v fdmc3612 : 10mq100ntrpbf c1s 1.5 vpwr p2 + - rj45 & xfmr smbj58a-13-f 0.1 p f 100v fdmc3612 : 10mq100ntrpbf c1s 1.5 vpwr p1 + - rj45 & xfmr (optional) (optional) TPS23861PW smbj58a-13-f 0.1 p f 100v fdmc3612 : 10mq100ntrpbf c1s 1.5 vpwr p3 + - rj45 & xfmr smbj58a-13-f 0.1 p f 100v fdmc3612 : 10mq100ntrpbf c1s 1.5 vpwr p4 + - rj45 & xfmr (optional) (optional) vpwr vdd
22 tps23861 slusbx9e ? march 2014 ? revised march 2016 www.ti.com product folder links: tps23861 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated overview (continued) 7.1.1 detailed pin description the following descriptions refer to the pinout and the functional block diagram. drain1-drain4: port 1-4 output voltage monitor and detect sense. used to measure the port output voltage, for port voltage monitoring, port-power-good detection and foldback action. detection probe currents also flow into this pin. the tps23861 uses an innovative 4-point technique in order to provide a reliable pd detection. detection is performed by sinking two different current levels via the drainn pin, while the pd voltage is measured from vpwr to drainn. the 4-point measurement provides the capability to distinguish between an ieee-standard-compliant pd and a capacitive or legacy load. if the port n is not used, drainn can be left floating or tied to agnd. gate1-gate4: port 1-4 gate drive output used for external n-channel mosfet gate control. at port turn on, it is driven positive by a low-current source to turn the mosfet on. gaten is pulled low whenever any of the input supplies are low or if an over-current timeout has occurred. gaten will also be pulled low if its port is turned off during fast shutdown. leave floating if unused. for a robust design, a current-foldback function limits the power dissipation of the mosfet during low resistance load or a short-circuit event. the foldback mechanism measures the port voltage across agnd and drainn to reduce the current-limit threshold as shown in figure 14 , figure 57 , and figure 58 . the fast overload protection is for major faults like a direct short. this forces down the current within the current limit in less than a microsecond. when icut threshold is exceeded while a port is on, a timer starts. during that time, linear current limiting makes sure the current will not exceed ilim combined with current-foldback action. when the timer reaches its t ovld (or t start if at port turn on) limit, the port shuts off. when the port current goes below i cut , the counter counts down at a rate 1/16 th of the increment rate, and it must reach a count of zero before the port can be turned on again. ksensa, ksensb: kelvin point connection used to perform a differential voltage measurement across the associated current sense resistors. ksensa is shared between sen1 and sen2, while ksensb is shared between sen3 and sen4. in order to optimize the accuracy of the measurement, the pcb layout (see figure 61 ) must be done carefully to minimize impact of pcb trace resistance. shtdwn: shutdown, active low. this pin is internally pulled up to vdd, with internal 1- s to 5- s deglitch filter. the port power priority register is used to determine which port(s) is (are) shut down in response to an external assertion of the shtdwn pin. the turn-off procedure is similar to a port reset or a reset command (reset register). note after a shtdwn cycle occurs, the i 2 c host should reinitialize the tps23861 register set according to the desired user configuration. more detail regarding use of the shtdwn pin to power off low priority ports can be obtained by consulting a texas instruments technical representative. reset: reset input, active low. when asserted, the tps23861 resets, turning off all ports and forcing the registers to their power-up state. this pin is internally pulled up to vdd, with internal 1- s to 5- s deglitch filter. external rc network can be used to delay the turn-on. there is also an internal power-on-reset which is independent of the reset input. note after reset pin de-assertion, there is a delay of approximately 20 ms before tps23861 can process i 2 c commands. for more information, refer to the application note tps23861 power-on considerations, slva723 .
23 tps23861 www.ti.com slusbx9e ? march 2014 ? revised march 2016 product folder links: tps23861 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated overview (continued) sen1- sen4: port 1-2 current sense input relative to ksensa, and port 3-4 current sense relative to ksensb. a differential measurement is performed using ksensa and ksensb kelvin point connection. it monitors the external mosfet current by use of either a 255-m (two 510 m in parallel) or a 250-m (four 1 in parallel) current-sense resistors connected to agnd. used by current foldback engine and also during classification. can be used to perform load current monitoring via a/d conversion. note a classification is done while using the external mosfet so performing a classification on more than one port at the same time is possible without exceeding dissipation in the tps23861. for the current limit with foldback function, there is an internal 2- s analog filter on the sen1-4 pins to provide glitch filtering. for measurements through an a/d converter, an anti-aliasing filter is present on the sen1-4 pins. this includes the port-powered current monitoring and disconnect. if the port is not used, tie senn to agnd. vdd: 3.3-v logic power supply input. vpwr: high-voltage power supply input. nominally 48 v. 7.1.2 i 2 c detailed pin description ain: used to program the i 2 c slave device address. this pin is internally pulled up to vdd. see i 2 c slave address and auto bit programming for more details. aout: used to program the i 2 c slave device address for multiple devices. see i 2 c slave address and auto bit programming for more details. aout is open drain. a3: i 2 c a3 address input, used during normal operation and during slave address programming. this pin is internally pulled up to vdd. int: interrupt output. this pin asserts low when a bit in the interrupt register is asserted. this pin is updated between i 2 c transactions. this output is open-drain. interrupt functional diagram is shown in figure 43 . scl: serial clock input for i 2 c bus. requires an external pull-up resistor to vdd. sdai: serial data input for i 2 c bus. requires an external pull-up resistor to vdd. this pin can be connected to sdao for non-isolated systems. see figure 50 . sdao: open-drain i 2 c bus output data line. requires an external resistive pull up. the tps23861 uses separate sdao and sdai lines to allow optoisolated i 2 c interface. sdao can be connected to sdai for non-isolated systems. note both vpwr and vdd must be present for proper system level i 2 c operation.
24 tps23861 slusbx9e ? march 2014 ? revised march 2016 www.ti.com product folder links: tps23861 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated 7.2 functional block diagram copyright ? 2016, texas instruments incorporated port 2-4 analog control functions port 1 analog control functions range select 14-bit adc (current) 2x power idet = 160/ 270/ 540ua iclass internal rails good temp vee vds bit 4:1 mux v48 ptat diodes analog bit mux range select variable averager vdisco gm driver drain1 4 port diff amp v48 drain1 4 vport foldback schedulers fast ishort protection gatex enable senx ain ilim 320-hz lpf iport bit rst to blks i2c interface 1 byte ee nvm 7-bit address/including state of a3 pin ain/aout mux processor scl watchdog bus if class current limit class port voltage control aout sdai sdao scl vdd uvlo vdd vpwr reset shtdwn pg shtdwn direct shutdown for ports drainx 18 v ksensea,b pg shtdwn int a3 analog test ain 0.255 shtdwn/por vpwr discrete io conditioners register file 14-bit adc (voltage) variable averager dv/dt ramping control rapid overload recovery pd load rst block
25 tps23861 www.ti.com slusbx9e ? march 2014 ? revised march 2016 product folder links: tps23861 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated 7.3 feature description 7.3.1 detection resistance measurement the detect resistance can be measured and reported in the port n detect resistance register . fourteen bits of resistance information are reported in two bytes. useful range of measurement is 500 to 55 k . resolution (1 lsb) is approximately 11 . measurement repeatability is on the order of 200 . additionally, in the msb of the resistance register (port n resistance: msbyte) the rsn field reports whether a low-resistance circuit, open circuit or mosfet short fault is detected. before detection begins, the tps23861 backs-off for up to 400 ms to allow the port voltage to drop below 2.8 v. this will allow any pd on the port to reset prior to an attempt to detect, classify and apply power to the pd. table 1. rsn field encoding rsn1 rsn0 detect status r step bit weight 0 0 other 11.0966 /bit 0 1 low ( < 2 k ) additional detect 4.625 /bit 1 0 open circuit n/a 1 1 mosfet short fault n/a 7.3.2 physical layer classification whether one or two classification events will be executed depends on the operating mode and the value of the teclenn field in the two-event classification register. see device functional modes for details. see figure 38 and figure 39 for illustrations of the voltage on the power interface (pi) during single-event (802.3af) and 2-event (802.3at) classification.
26 tps23861 slusbx9e ? march 2014 ? revised march 2016 www.ti.com product folder links: tps23861 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated figure 38. 802.3af with classification figure 39. p802.3at with classification powered on 2.8 10 15.5 20.5 1 st class 2 nd class 1 st mark 2 nd mark voltage xx xx xxxxxxxxxxxx xxxxxxxxxxxx xxxxxxxxx xxxxxxxxx xxxxxxxxx xxx xxx xxxxxxx xxxxxxx xxxxxxx xxx xxx xxx powered on 2.8 10 15.5 20.5 802.3 optional classification free format transition four point detection voltage
27 tps23861 www.ti.com slusbx9e ? march 2014 ? revised march 2016 product folder links: tps23861 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated 7.3.3 class and detect fields the results of the detection cycle and classification cycle are each stored in a 4-bit field for each port in the detect pn and class pn fields of the port n status register. the results of a detection and classification event are encoded as follows. table 2. detect pn field encoding detect pn detect status 0000 unknown (por value) 0001 short circuit ( < 500 ) 0010 reserved 0011 resistance too low 0100 resistance valid 0101 resistance too high 0110 open circuit 0111 reserved 1000 mosfet fault 1001 legacy detect 1010 capacitance measurement invalid: detect measurement beyond clamp voltage 1011 capacitance measurement invalid: insufficient v measured 1100 capacitance measurement is valid, but outside the range of a legacy device. table 3. class pn field encoding class pn classification status 0000 unknown 0001 class 1 0010 class 2 0011 class 3 0100 class 4 0101 reserved ? read as class 0 0110 class 0 0111 overcurrent 1000 class mismatch a class mismatch can occur only during two-event classification. if the classification statuses for the first and second event are different, and the second classification status is not ? overcurrent ? , the classification status will be set to class mismatch. if the status of the first classification event is ? overcurrent ? , the classification status is set to ? overcurrent ? in the class pn field, and there will be no second classification event in any case. if in auto mode, the port will not power on automatically, but it still can be powered on through the power enable register.
28 tps23861 slusbx9e ? march 2014 ? revised march 2016 www.ti.com product folder links: tps23861 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated 7.3.4 register state following a fault following an icut, ilim or inrush fault on port n, the port is shut off, and the appropriate fault bit is set in the fault event register or start/ilim event register. in addition, the following registers are affected. ? the pgn and pen in the power status register are cleared. ? the clscn and detcn bits in the detection event register are cleared. ? the corresponding port n status registers are cleared. ? the pgcn and pecn bits in the power event register are set. ? the port n voltage registers is cleared. 7.3.5 disconnect the tps23861 supports dc disconnection. disconnect threshold and timing are set using the dcthn field in the disconnect threshold register and the tdis field in the timing configuration register respectively. following a disconnect event on port n, the following registers are affected. ? the disfn bit in the fault event register is set. ? the pgn and pen in the power status register are cleared. ? the clscn and detcn status bits in the detection event register are cleared. ? the corresponding port n status registers are cleared. ? the pgcn and pecn bits in the power event register are set. ? the corresponding port n voltage registers are cleared. 7.3.6 disconnect threshold the disconnect current range is selectable through the dcthn 2-bit fields in the disconnect threshold register. the encoding of the dcthn fields is presented in table 4 . table 4. dcthn field encoding dcthn field disconnect threshold, ma 00 7.5 01 15 10 30 11 50 7.3.7 fast shutdown mode the tps23861 responds to a low level on the shtdwn pin by immediately turning off all ports preconfigured as low priority through the fsen bits in the port power priority register. reaction time is typically 2 s. if an fsen bit is set while the shtdwn pin is low, the corresponding port is turned off and reset.
29 tps23861 www.ti.com slusbx9e ? march 2014 ? revised march 2016 product folder links: tps23861 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated 7.3.8 legacy device detection legacy pds which are not compliant with ieee 802.3at can be identified on port n under control of the legmod field in the legacy detect mode register. two modes of legacy detection are supported. when legmodn = 10, port n is probed for ieee 802.3at-based compliance (based on resistance measurement) followed by a capacitance-based detection scheme for legacy devices. when legmodn= 01, port n performs a capacitance- based detection scheme only. this allows the host to probe for a potential legacy pd without pre-charging the pd capacitance before trying to measure the value of the capacitance. to measure capacitance, a fixed charge is injected into the power interface (pi) and the voltage difference induced by the charge is measured and reported in the port n detect voltage difference registers. the capacitance is inversely proportional to the voltage difference. the voltage difference is compared against thresholds to accept capacitance values above 6 f pursuant to the qualifications which follow. the port n detect voltage difference register consists of two contiguous bytes in the i 2 c addressable register space. together these registers contain a 12-bit unsigned representation of the voltage difference along with a 4- bit status field named vdsn. when vdsn = 0001 the voltage-difference value represents a valid measurement. the capacitance measurement may fail due to an excessively small or large capacitance, or an input capacitance which cannot be discharged because it is behind a diode. these cases are reported in the vdsn field as well as in the detect pn field in the port n status registers. see table 5 . table 5. capacitance measurement characteristics and capabilities parameter conditions value unit minimum measurable capacitance maximum 500-k parallel resistance; maximum measurement voltage of 16.5 v at port 6.1 f maximum measurable capacitance minimum 17-k parallel resistance 100 f maximum measurable capacitance minimum 10-k parallel resistance 67 f nominal port charging current 540 a nominal measurement time 150 ms minimum voltage at port for commencement of measurement 0.4 v maximum voltage at port for commencement of measurement 2.4 v duration of port-discharge period first discharge attempt 250 ms duration of port-discharge period second discharge attempt 500 ms maximum voltage at port at the beginning or end of measurement 16.5 v a resistance in parallel with the capacitance at the input of the pd affects the accuracy of the capacitance- measurement algorithm. a parallel resistance causes the capacitance on the port to appear higher. this fact is reflected in table 5 . capacitance up to 100 f can be measured with a parallel resistance as low as 17 k , whereas if the parallel resistance is as low as 10-k , capacitance up to 67 f can be measured. the voltage on the port must be in the range of 0.4 v to 2.4 v to begin capacitance measurement. this voltage as measured at the pse includes the voltage drops across any diodes in the path of the capacitance. if the voltage measured is too high (due to charge on the pd capacitance), the tps23861 makes two attempts to discharge the port by applying a 100-k load across the port. the first discharge attempt is 250-ms duration; the second attempt 500 ms. note it may not be possible to discharge the pd capacitance rapidly if the capacitance is on the other side of a diode.
30 tps23861 slusbx9e ? march 2014 ? revised march 2016 www.ti.com product folder links: tps23861 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated if the capacitance-measurement algorithm is unable to discharge the port to less than 2.4 v after two attempts, the algorithm terminates the attempt to measure port capacitance, and report an unable to achieve 2.4 v to take first measurement status in the vdsn field of the port n detect voltage difference registers. a status of capacitance measurement invalid: insufficient v measured is reported in the port n status registers. a status of unable to discharge pd input capacitance to 2.4 v before timeout , is reported in the vdsn field of the port n detect voltage difference registers. the host has the option of imposing a longer discharge time and retrying. erratic results may be obtained when performing legacy detect in semi-auto mode due to the repeated charging of the load. if the capacitive load is behind a diode or is in parallel with a high resistance, the capacitor may eventually charge beyond 2.4 v, and the capacitance measurement fails. manual mode is recommended for legacy detect when there is no information about the load, or if the load input capacitance charges beyond 2.4 v in semi-auto mode. if the port is open or a small capacitance is present on the port, the port voltage rises quickly when the capacitance-measuring current is applied. the voltage on the port is limited to approximately 18 v by an internal clamp. a status of capacitance measurement invalid: detect measurement beyond clamp voltage is reported in the detect pn field of the port n status registers. depending on the size of the small capacitance, a status of first measurement exceeds v det-clamp (min) or second measurement exceeds v det-clamp (min) is reported in the vdsn field of the port n detect voltage difference registers. if a large capacitance or short circuit is present on the port, the port voltage will not change sufficiently over the port charging time to assure a reliable measurement. in this case, a status of capacitance measurement invalid: insufficient v measured is reported in the port n status registers, and a status of v < 0.5 v (insufficient signal) or unable to achieve 0.4v to take first measurement before timeout is reported in the vdsn field of the port n detect voltage difference registers. legacy detect is an exceptional condition which warrants special handling by the host system. consequently, legacy-detect operation will not be fully supported in auto mode. if a legacy device is detected during detection in any mode of operation, the detect status is reported as legacy detect in the port n status register detect pn field. it is up to the host to power on the port. if a port is in auto mode, legacy detection is enabled and a legacy device is detected, the detect status is reported as legacy detect in the port n status registers detect pn field, but the port will not power on automatically. in this respect, operation of the port is identical to the semi-auto mode. in general, it is expected that a legacy device will not respond to a request for classification. therefore, if the port is in semi-auto or auto mode and detect status is legacy detect, the pse will not automatically initiate a classification cycle even if the clen bit is set. on the other hand, if legmod = 10, the tps23861 is operating in semi-auto or auto mode, classification is enabled via the clen bit, and a resistance valid detect status is returned in response to a standard resistance detection cycle, the tps23861 follows the standard resistance detection cycle with a classification cycle. furthermore, following classification, if in auto mode, if the classification status is not unknown, class mismatch or overcurrent, the port automatically powers up. it is possible to initiate a classification cycle under manual control using the clen bit in the detect/class enable register or the rcln bit in the detect/class restart register or power on the port under manual control using the pwonn bit in the power enable register. if legmodn = 10, and a resistance valid detect status is returned in response to a standard resistance detection cycle the tps23861 will not attempt to measure capacitance on the pi.
31 tps23861 www.ti.com slusbx9e ? march 2014 ? revised march 2016 product folder links: tps23861 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated 7.3.9 vpwr undervoltage and uvlo events this section lists the behavior of vpwr undervoltage and uvlo events when the voltage at the vdd pin is uninterrupted. when the voltage at the vpwr pin falls below v puv_f the following occurs. ? the vpuv bit in the supply event register is set. ? all ports are shut off. ? for ports that are shut off the corresponding pgcn and pecn bits in the power event register is set and the pgn and pen bits in the power status register are cleared. ? the following registers are cleared. ? detection event register ? fault event register ? start/ilim event register ? port n status register ? detect/class enable register note when the voltage at the vpwr pin falls below v uvlopw_f the following occurs. ? both the vpuv and vduv bits in the supply event register is set ? all ports are shut off ? all registers are set to their power-on/reset state
32 tps23861 slusbx9e ? march 2014 ? revised march 2016 www.ti.com product folder links: tps23861 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated 7.3.10 timer-deferrable interrupt support a programmable timer is provided with range selectable from 10 ms to 150 ms in 10 ms increments. timer duration is programmed via the four-bit field tmr [3:0] in the interrupt timer register. non-critical interrupts will be deferred from asserting an interrupt on the int pin until the timer times out. critical interrupts such as faults will not be affected by the state of this timer. critical vs. deferrable interrupts are identified in table 6 . the behavior of the various interrupt enable bits is not affected by the timer function. table 6. timer-deferrable interrupt interrupt bit function critical or deferrable supf supply or thermal fault critical strtf start fault deferrable ifault icut or ilim fault critical clasc a classification event occurred deferrable detc a detection event occurred deferrable disf a disconnect event occurred deferrable pgc power good status change deferrable pec power enable status change deferrable if the counter is loaded with 0000 (por state) the counter will not count, and no interrupts will be deferred. that is, this function will be disabled.
33 tps23861 www.ti.com slusbx9e ? march 2014 ? revised march 2016 product folder links: tps23861 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated 7.3.11 a/d converter and i 2 c interface the tps23861 features five multi-slope integrating converters. each of the first four converters is dedicated to current measurement for one port and is operated independently to perform measurements. the converters are used for current monitoring (100 ms averaged) and disconnect. the fifth converter is shared between all four ports for detection (conversion time set by mains bit), port voltage monitoring, power good status and fet short detection (1 ms for all). it is also used for general-purpose measurements including input voltage (1 ms) and temperature. the a/d converter type used in the tps23861 differs from other types of converters in that it converts while the input signal is being sampled by the integrator, resulting in reduced conversion time and providing inherent filtering over the conversion period. the typical conversion time of the current converters is 800 s. digital averaging is used to provide a port current measurement integrated over a 100-ms time period. note an anti-aliasing filter is present for current and voltage monitoring. port current conversions are performed continuously. powered device (pd) detection is performed by averaging 16 consecutive samples providing significant rejection of noise at 50/60-hz line frequency. the total time for the 16 samples can be set to 20 ms or 16.7 ms by the mains bit to correspond to the local mains frequency. the fifth converter continuously measures drain voltages from one port to the next one, updating internal registers used for power good status and fet short detection, unless a command is received to perform a specific measurement. also, when the port is powered on, the t start timer (used during pd power-on inrush) must expire before any current or voltage a/d conversion can begin for the first four converters. figure 40 illustrates read and write operations through i 2 c interface. the two-data-bytes-read operation is applicable to a/d conversion results. it is also possible to perform an i 2 c write operation to many tps23861 devices at same time. the slave address during this broadcast access is 0x30. the tps23861, using the int pin, supports the smbalert protocol. when int is asserted low, if the bus master controller sends the alert response address, the tps23861 responds providing its device address on the sda line and releases the int line. if there is a collision between two tps23861 devices responding simultaneously, then the device with the lower address wins arbitration and responds first, by use of sdai and sdao lines. an i 2 c watchdog timer is also available on the tps23861, which monitors the i 2 c clock line in order to prevent hung software situations that could leave ports in a hazardous state. the timer can be reset by either edge on the scl line. when enabled, if the watchdog timer expires, all ports are turned off and wds bit is set. the nominal watchdog time-out period is 2 seconds. see i 2 c watchdog register for more details on the subject. note when a stop condition is detected on the i 2 c bus after having at least received the command byte, the tps23861 stores the command byte in an internal register. note when using the i 2 c interface the host software should wait 22 ms minimum after a reset to ensure valid i 2 c transactions.
34 tps23861 slusbx9e ? march 2014 ? revised march 2016 www.ti.com product folder links: tps23861 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated this content can be later used as a register address pointer during next quick read cycle register access. see figure 40 . this internal register is cleared at power on or through the reset pin. figure 40. i 2 c/smbus interface read and write protocol write cycle a6 a5 a4 a3 a2 a1 a0 r/w d7 d6 d5 d4 d3 d2 d1 d0 start bit slave address r/w=0 r/w bit data from host to slave stop bit ack bit ack bit ack bit c7 c6 c5 c4 c3 c2 c1 c0 command code a6 a5 a4 a3 a2 a1 a0 r/w a6 a5 a4 a3 a2 a1 a0 r/w d7 d6 d5 d4 d3 d2 d1 d0 r/w bit start bit slave address r/w=0 command code slave address r/w=1 r/w bit data from slave to host ack bit ack bit ack bit nack bit stop bit c7 c6 c5 c4 c3 c2 c1 c0 d7 d6 d5 d4 d3 d2 d1 d0 1 data byte read cycle 2 data byte read cycle sdao a6 a5 a4 a3 a2 a1 a0 r/w a6 a5 a4 a3 a2 a1 a0 r/w d7 d6 d5 d4 d3 d2 d1 d0 r/w bit start bit slave address r/w=0 command code slave address r/w=1 r/w bit lsbyte data from slave to host ack bit ack bit bit sdai nack bit stop bit c7 c6 c5 c4 c3 c2 c1 c0 ack bit ack d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 sdao sdai sdao sdai repeated start bit repeated start bit msbyte data from slave to host a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 slave address r/w=1 r/w bit data from slave to host start bit ack bit nack bit stop bit d7 d6 d5 d4 d3 d2 d1 d0 quick read cycle (latest addressed register) sdao sdai a6 a5 a4 a3 a2 a1 a0 ara slave address r/w=1 r/w bit slave address from slave to host start bit ack bit nack bit stop bit a6 a5 a4 a3 a2 a1 a0 alert response sdao sdai a6 a5 a4 a3 a2 a1 a0 r/w r/w
35 tps23861 www.ti.com slusbx9e ? march 2014 ? revised march 2016 product folder links: tps23861 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated 7.3.12 independent operation when the bit is set the tps23861 operates as a fully automatic pse in compliance with ieee 802.3at when the auto bit is set as described in i 2 c slave address and auto bit programming section. fully automatic operation means that the tps23861 operates as a power-over-ethernet four-port pse without any connection to a host system via the i 2 c bus. generally speaking, when the bit is set, most specialized features of the tps23861 are disabled. note the state of the auto bit is read only following power on, hardware reset ( reset pin) or writing a 1 to the resal bit in the reset register. if the auto bit is set and the tps23861 is connected to a host over the i 2 c bus, the host may change the register settings any time after power up, including changing operating mode. when the auto bit is set, the state of tps23861 following power up is summarized below. ? the clen and detn bits in the detect/class enable register is set. consequently, detect and classification is performed before any power on. ? the dcden bit in the disconnect enable register is set, enabling automatic disconnection. ? the teclenn bits in the two-event classification register is set to 0b01. consequently, if a class 4 pd is recognized during the classification cycle, ? the tps23861 initiates a second physical-layer classification event. ? the poepn bit in the poe plus register is set, employing the 2x curve for i lim . ? the icut port n fields in the icutnm config registers will be set to 0b110 corresponding to 645 ma. ? if a class 0, 1, 2 or 3 pd is recognized during the classification cycle, ? there is no second physical-layer classification event. ? the poepn bit is cleared so the tps23861 employs the 1x foldback curve for i lim . ? a value of 374 ma is used for icut. ? the port n mode field in the operating mode register is set to auto (0 11) for all four ports. consequently, ? detection, classification and power up occurs in sequence, automatically and independently for each port. ? following a valid one- or two-event physical layer classification, the tps23861 applies power to a port subject to the inrush-current foldback protection curve in figure 57 . . ? the fsen bits in the port power priority register is set. consequently, all ports are shut down in response to a low level on the shtdwn pin. ? the legmodn fields in the legacy detect mode register is set to 00. consequently, legacy pd devices not compliant with ieee 802.3at will not be detected. ? the general mask 1 register is set to its standard power-on-reset value 0x80. consequently, ? interrupts are enabled. ? during detection a/d conversions of the detect voltage occurs at a rate of 800 per second. ? classification levels are determined as if a 255-m resistor is used for the current-sense resistor. note if a 250-m resistor is used, the classification thresholds shifts slightly, but remains compliant with ieee 802.3at. ? the interrupt enable register is set to 0xe4, enabling the following interrupts ? supen ? supply event fault enable bit. ? strten ? start fault enable bit. ? ifen ? icut or ilim fault enable bit. ? disen ? disconnect event interrupt enable bit. ? any register not explicitly referenced above is set to its default power-on-reset value according to table 10 .
36 tps23861 slusbx9e ? march 2014 ? revised march 2016 www.ti.com product folder links: tps23861 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated 7.3.13 i 2 c slave address and auto bit programming note when using the i 2 c interface the host software should wait 22 ms minimum after a reset to ensure valid i 2 c transactions. note please note eeprom endurance of 25 write cycles. writing to the eeprom more than this may result in erratic behavior. the tps23861 includes a means to program in eeprom the following two fields: ? a seven bit i 2 c slave address for operation with a host processor. ? auto bit which allows the tps23861 to operate independently without a host processor. the benefits this approach include: ? up to 125 similar devices become addressable. ? provides a high level of flexibility. ? helps to resolve conflicts with other peripherals on same i 2 c bus. ? the i 2 c address can be programmed at production subassembly module level or motherboard level. ? allows a simple approach to field-installed upgrades or expansions to pse systems. ? no physical address line required, no bank selection required. ? smaller package. no address line pins and no auto pin. note for compatibility with legacy systems, the module a3 bank addressing is provided by use of the a3 input pin. as shown in figure 41 , the initial i 2 c address programming access is established by a local daisy chain chip select connection between multiple tps23861 devices. the ain pin plays the role of a ? moving chip select ? during address programming. note global write command including an unlock code (aah) is required in order to write to the i 2 c slave address register.
37 tps23861 www.ti.com slusbx9e ? march 2014 ? revised march 2016 product folder links: tps23861 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated figure 41. i 2 c slave address and auto bit programming circuit scl 14 13 12 11 10 9 8 7 6 5 4 3 2 1 vdd scl sdai sdao dgnd sen3 drain3 gate3 ksensb sen4 drain4 gate4 15 16 17 18 19 20 21 22 23 24 25 26 27 28 vpwr n/c aout ain shtdwn a3 agnd gate2 drain2 sen2 ksensa gate1 drain1 sen1 reset int u2 14 13 12 11 10 9 8 7 6 5 4 3 2 1 vdd scl sdai sdao dgnd sen3 drain3 gate3 ksensb sen4 drain4 gate4 15 16 17 18 19 20 21 22 23 24 25 26 27 28 vpwr n/c aout ain shtdwn a3 agnd gate2 drain2 sen2 ksensa gate1 drain1 sen1 reset int u1 sdai 14 13 12 11 10 9 8 7 6 5 4 3 2 1 vdd scl sdai sdao dgnd sen3 drain3 gate3 ksensb sen4 drain4 gate4 15 16 17 18 19 20 21 22 23 24 25 26 27 28 vpwr n/c aout ain shtdwn a3 agnd gate2 drain2 sen2 ksensa gate1 drain1 sen1 reset int un-1 14 13 12 11 10 9 8 7 6 5 4 3 2 1 vdd scl sdai sdao dgnd sen3 drain3 gate3 ksensb sen4 drain4 gate4 15 16 17 18 19 20 21 22 23 24 25 26 27 28 vpwr n/c aout ain shtdwn a3 agnd gate2 drain2 sen2 ksensa gate1 drain1 sen1 reset int un v dd all devices respond to global address 30h regardless of the state of the a3 pin. if u1 or u2 is programmed with i 2 c address [a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 ] the device will respond to the i 2 c address [a 7 a 6 a 5 a 4 0 a 2 a 1 a 0 ] because the a3 pin is tied low. if un-1 or un is programmed with i 2 c address [a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 ] the device will respond to the i 2 c address [a 7 a 6 a 5 a 4 1 a 2 a 1 a 0 ] because the a3 pin is tied high. ain-aout daisy-chain connection allows the i 2 c address of each device to be programmed separately
38 tps23861 slusbx9e ? march 2014 ? revised march 2016 www.ti.com product folder links: tps23861 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated the sequence during address programming is as follows: ? global write command including an unlock code (aah) and a temporary common slave address (any address other than 30h) is sent to all i 2 c devices through the broadcast address, 30h. ? all tps23861 devices respond to the broadcast address 30h regardless of the state of the a3 pin. when the three-byte sequence is correctly decoded, 1. each tps23861 has a new i 2 c address determined by the programmed temporary slave address with bit 3 equal to the state of the a3 pin. 2. all tps23861 devices force low the aout output. for example, if a temporary common slave address of 20h is written to one device with a3 low and one with a3 high, the device with a3 low will respond to i 2 c address 20h and the device with a3 high responds to i 2 c address 28h. ? the first tps23861 device being selected is the only one having its ain pin at logic high level (u1 in figure 41 ). ? using the temporary slave address, write the new 7-bit device address in the i 2 c slave address register. see data format below. note the sla3 slave address bit follows the logic level of a3 input pin, as detailed for i 2 c slave address register. bits d7 d6 d5 d4 d3 d2 d1 d0 bit name auto 7-bit i 2 c address ? the first slave accepts the new address, then forces its aout output pin to high level and automatically locks the access to its slave address register. it also stores permanently its new slave address into eeprom. ? the same procedure is repeated for the next slave device, which has just detected that its ain input has become high. ? this is repeated until all slaves have been reprogrammed. ? the host can then interrogate each slave, one by one, in order to validate their new address. note during the address programming procedure if the slave has not received its new address within a timeout period (around 100 ms), it goes back to the initial slave address (before the address programming sequence was initiated); it locks its address register and releases its aout output. ? bit 7 of the 8-bit transfer (auto) defines if the controller operates independently (no host processor) as an automatic pse. the state of this bit is monitored only immediately following a power-on reset, writing a 1 to the resal bit of the reset register, or after the reset input has been activated. the impact of that bit state on registers after reset is reflected in the table 10 (reset state column) and is referred to as ? a ? . note after programming a new i 2 c slave address to register 0 11, a 100 ms delay is recommended before trying to perform a read check.
39 tps23861 www.ti.com slusbx9e ? march 2014 ? revised march 2016 product folder links: tps23861 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated figure 42. i 2 c/smbus interface slave address programming protocol global write cycle: unlock the address register 0 1 1 0 0 0 0 w 0 d6 d5 d4 d3 d2 d1 d0 start bit 7-bit global address r/w=0 r/w bit temporary common slave address stop bit ack bit ack bit ack bit c7 c6 c5 c4 c3 c2 c1 c0 unlock code sdao sdai aout u1 aout un-1 aout un .. . slave #1 i 2 c address programming w d7 d6 d5 d4 d3 d2 d1 d0 start bit temporary common slave address r/w bit new slave address stop bit ack bit ack bit ack bit 0 0 0 1 0 0 0 1 slave address command r/w=0 ... slave #n i 2 c address programming w d7 d6 d5 d4 d3 d2 d1 d0 r/w bit new slave address stop bit ack bit ack bit ack bit slave address command ... sdao sdai aout u1 aout un-1 aout un .. . sa6 sa5 sa4 sa3 sa2 sa1 sa0 start bit temporary common slave address r/w=0 sa6 sa5 sa4 sa3 sa2 sa1 sa0 0 0 0 1 0 0 0 1 t stp_aout
40 tps23861 slusbx9e ? march 2014 ? revised march 2016 www.ti.com product folder links: tps23861 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated figure 43. interrupt logic functional diagram q7 q6 q5 q4 d ck q r r supply event supply event cor 0x0bh clrain (clear all interrupts) (0x1ah) supf interrupt bit 7 (0x00h) supen interrupt enable (0x01h) clrain (clear all interrupts) (0x1ah) clinp (clear interrupt pin) (0x1ah) q3 q2 q1 q0 d ck q r r port start fault start event cor 0x09h clrain (clear all interrupts) (0x1ah) strtf interrupt bit 6 (0x00h) strten interrupt enable (0x01h) clrain (clear all interrupts) (0x1ah) clinp (clear interrupt pin) (0x1ah) q7 q6 q5 q4 port power good status change pgc interrupt bit 1 (0x00h) pgsen interrupt enable (0x01h) q3 q2 q1 q0 d ck q r r port power enable status change pwr enable event cor 0x03h clrain (clear all interrupts) (0x1ah) pec interrupt bit 0 (0x00h) pesen interrupt enable (0x01h) clrain (clear all interrupts) (0x1ah) clinp (clear interrupt pin) (0x1ah) pwr good event logic hi ck q r int inten (interrupt pin enable (0x17h) port disconnect event detection cycle classification cycle icut or ilim fault copyright ? 2016, texas instruments incorporated
41 tps23861 www.ti.com slusbx9e ? march 2014 ? revised march 2016 product folder links: tps23861 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated 7.4 device functional modes four operating modes are defined as follows. operating mode is controlled for each port through the port n mode field in the operating mode register. operating mode codes appear in operating mode register . 7.4.1 off port n will not detect, classify or power on. when the operating mode of port n is set to off the following takes place. ? port voltage and current are monitored continuously. the results are reported in the port n voltage and port n current registers. ? the clscn and the detcn bits in the detection event register are cleared. ? the port n status register is cleared. ? the clen and the deten bits in the detect/class enable register are cleared. ? the disfn and the icutn bits in the fault event register are cleared. ? the ilimn and strtn bits in the start/ilim event register are cleared. ? if the port was powered on when the operating mode is set to off, the port is shut off, and the following occurs. ? the pgcn and the pecn bits in the power event register are set. ? the pgn and pen bits in the power status register are cleared. 7.4.2 manual note in order to meet the ieee 802.3at standard, pwonn bit should be set within 22 ms after classification is completed if two-event classification is applied. there is no automatic change of state. a single detection or classification event may be initiated by writing to the appropriate bit of the detect/class restart register which is a pushbutton register. furthermore, setting the deten bit initiates one detect cycle for port n; setting the clen bit initiates one classify cycle for port n. the number of classification events depend on the classification status of the first classification event and the setting of the teclenn field as shown in table 7 . table 7. number of classification events in manual mode classification status of first classification event value of teclenn total number of classification events class 0, class 1, class 2 or class 3 xx one class 4 x0 one x1 two in manual mode, writing to the pushbutton pwonn bit powers on port n immediately. note in manual mode, the icutn and poepn fields are not set automatically. they must be set by the host. furthermore, there is no cool-down period in manual mode.
42 tps23861 slusbx9e ? march 2014 ? revised march 2016 www.ti.com product folder links: tps23861 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated 7.4.3 semi-auto no activity takes place on the port until the deten bit in the detect/class enable register is set. when deten is set, port n automatically performs detection. if a valid pd is detected and clen is set, the port initiates a classification cycle. the classification cycle is single-event if a class 0, 1, 2 or 3 pd is recognized. if the first classification event returns a class 4 signature, a second classification event is initiated depending on the setting of the teclenn field in the two-event classification register. the cycle of detect, then classification repeats continuously. powering on the port requires writing to the pushbutton pwonn bit in the power enable register. the port powers on meeting the ieee t p(on) requirement to power on within 400 ms of the end of a valid detection. depending on the timing of the pwonn command, the controller may initiate a new detect and (if clen is set) classification sequence before powering on the port if required to meet the t p(on) requirement. if the final detect is invalid, or if the final classification returns overcurrent or class mismatch, the port will not power on and the strtn bit is set in the start/ilim event register. for turn-on sequencing see push-button power on response . note in semi-auto mode, the icutn and poepn fields are not set automatically. they must be set by the host. following a power-off command, disconnect or shutdown due to a start, icut or ilim fault, the port powers off. following a shutdown due to a start, ilim or icut fault, the tps23861 enters into a cool-down period. during the cool-down period any port power on command using power enable command is ignored. the length of the cool- down period is set in the cldn field of the cool down/gate drive register. after the end of the cool-down period the tps23861 initiates a detect cycle and continues semi-automatic operation. note ti recommends using this reference code to develop your software http://www.ti.com/product/tps23861/toolssoftware
43 tps23861 www.ti.com slusbx9e ? march 2014 ? revised march 2016 product folder links: tps23861 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated 7.4.4 auto in auto mode the tps23861 automatically cycles the port through detection, classification and power on. the icut and poep fields are set automatically based on the classification status. if a class 0, 1, 2 or 3 pd is recognized, icutn is set to 000 (374 ma) and the poepn bit is cleared. if a class 4 pd is recognized, icutn is set to 110 (645 ma) and the poepn bit is set. auto mode and the auto bit are related, but are not identical. when the bit is set, all ports are placed in auto mode; additionally, several other registers are set. see independent operation when the bit is set section. following a power-off command, disconnect or shutdown due to a start, icut or ilim fault, the port powers off. following port power off due to a power off command or disconnect, the tps23861 continues automatic operation starting with a detection cycle (if deten is set). if the shutdown is due to a start, icut or ilim fault, the tps23861 enters into a cool-down period. during the cool-down period any port power-on command using power enable command is ignored. the length of the cool-down period is set in the cldn field of the cool down/gate drive register. after the end of the cool-down period the tps23861 continues automatic operation starting with a detection cycle, assuming deten is set. the tps23861 will not automatically apply power to a port, even if operating mode is set to auto, under the following circumstances. ? the detect status is not resistance valid. this means that the deten bit must be set in order to power on in auto mode. note a write to the deten bit or clen bit will not stick if the port is in off mode. ? if the classification status is overcurrent, class mismatch or unknown. the tps23861 starts in auto mode after a power-on reset or when the reset pin is de-asserted. when a valid pd is connected as tps23861 comes out of reset, then the ports will sequence through detection, classification, and power on as shown in figure 44 . staggered port power on prevents the sudden inrush of current from the vpwr supply when multiple pds are already connected.
44 tps23861 slusbx9e ? march 2014 ? revised march 2016 www.ti.com product folder links: tps23861 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated figure 44. port sequencing after reset pin de-assertion
45 tps23861 www.ti.com slusbx9e ? march 2014 ? revised march 2016 product folder links: tps23861 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated (1) response to a push-button power on. 7.4.5 push-button power on response the port behavior of the tps23861 to a commanded power on from the push-button register varies depending upon both the detect and class enable registers. table 8. summarized response (1) operating mode detect en bit class en bit port behavior off x x port does not power on manual x x port immediately powers on semi-auto 0 0 port does not power on 1 0 port powers on after completion of next good detect 0 1 port does not power on 1 1 port powers on after completion of next good detect and classification auto x x pushbutton power on ignored. port follows auto mode rules figure 45. semi-auto sequenced turn on
46 tps23861 slusbx9e ? march 2014 ? revised march 2016 www.ti.com product folder links: tps23861 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated (1) conditions that set start fault. 7.4.6 tstart indicators of detect and class failures the start fault indicator reports additional problems in semi-auto and auto modes to the host. this notifies the host that the pse encountered a problem and was unable to turn the port on. the interrupt pin activates when the tstart mask is enabled and one of these fault conditions occur. the conditions are described in table 9 . table 9. detect and class failure indicators (1) operating mode fault condition off none manual overcurrent condition at the end of t start time period semi-auto overcurrent condition at the end of t start time period detect not valid class unknown class mismatch class overcurrent auto overcurrent condition at the end of t start time period detect not valid class unknown class mismatch class overcurrent 7.4.7 device power on initialization at device power on and after vdd and vpwr exceed v uvddr and v uvlopw_r respectively, tps23861 initializes for t por . during this time tps23861 will not respond to i 2 c commands. wait approximately 20 ms after t por , before sending i 2 c commands.
47 tps23861 www.ti.com slusbx9e ? march 2014 ? revised march 2016 product folder links: tps23861 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated (1) bits labeled " r " are reserved. undesirable behavior may result if the value of these bits are changed from the reset value. (2) bits labeled ? a ? assume the state of the bit programmed into register 0x11 after por. (3) this register is read/write during slave address programming when preceded by the unlock code. 7.5 register map ? i 2 c-addressable table 10. i 2 c-addressable register set summary (1) (2) cmd code register or command name i 2 c r/w data byte rst state field description 00 interrupt ro 1 1000,0000 supf strtf ifault clasc detc disf pgc pec 01 interrupt enable r/w 1 1aa0,0a00 supen strte n ifen clcen deen disen pgsen pesen 02 power event ro 1 0000,0000 power good status change power enable status change 03 cor 1 pgc4 pgc3 pgc2 pgc1 pec4 pec3 pec2 pec1 04 detection event ro 1 0000,0000 classification detection 05 cor 1 clsc4 clsc3 clsc2 clsc1 detc4 detc3 detc2 detc1 06 fault event ro 1 0000,0000 disconnect occurred icut fault occurred 07 cor 1 disf4 disf3 disf2 disf1 icut4 icut3 icut2 icut1 08 start/ilim event ro 1 0000,0000 ilim fault occurred start fault occurred 09 cor 1 ilim4 ilim3 ilim2 ilim1 strt4 strt3 strt2 strt1 0a supply event ro 1 0011,0000 tsd - vduv vpuv - - - - 0b cor 1 0c port 1 status ro 1 0000,0000 class p1 detect p1 0d port 2 status ro 1 0000,0000 class p2 detect p2 0e port 3 status ro 1 0000,0000 class p3 detect p3 0f port 4 status ro 1 0000,0000 class p4 detect p4 10 power status ro 1 0000,0000 pg4 pg3 pg2 pg1 pe4 pe3 pe2 pe1 11 i 2 c slave address ro (3) 1 1010,0000 auto sla6 sla5 sla4 sla3 sla2 sla1 sla0 12 operating mode r/w 1 aaaa,aaa a port 4 mode port 3 mode port 2 mode port 1 mode 13 disconnect enable r/w 1 0000,aaaa - - - - dcde4 dcde3 dcde2 dcde1 14 detect/class enable r/w 1 aaaa,aaa a cle4 cle3 cle2 cle1 dete4 dete3 dete2 dete1 15 port pwr priority r/w 1 aaaa,0000 fse4 fse3 fse2 fse1 - - - - 16 timing configuration r/w 1 0000,0000 tlim tstart ticut tdis 17 general mask r/w 1 1000,0000 inten - - mains - - r m250 18 detect/class restart wo 1 - rcl4 rcl3 rcl2 rcl1 rdet4 rdet3 rdet2 rdet1 19 power enable wo 1 - poff4 poff3 poff2 poff1 pwon4 pwon3 pwon2 pown1 1a reset wo 1 - clrain clinp - resal resp4 resp3 resp2 resp1 20 legacy detect mode r/w 1 0000,0000 legmod4 legmod3 legmod2 legmod1 21 two-event classification r/w 1 0a0a,0a0a teclen4 teclen3 teclen2 teclen1 27 interrupt timer r/w 1 0000,0000 r r r r tmr 3-0 29 disconnect threshold r/w 1 0000,0000 dcth4 dcth3 dcth2 dcth1 2a icut21 config r/w 1 0000,0000 - icut port 2 - icut port 1 2b icut43 config r/w 1 0000,0000 - icut port 4 - icut port 3 2c temperature ro 0000,0000 temperature (bits 7 to 0)
48 tps23861 slusbx9e ? march 2014 ? revised march 2016 www.ti.com product folder links: tps23861 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated register map ? i 2 c-addressable (continued) table 10. i 2 c-addressable register set summary (1) (2) (continued) cmd code register or command name i 2 c r/w data byte rst state field description 2e input voltage ro 2 0000,0000 input voltage: lsbyte 2f ro 0000,0000 - - input voltage: msbyte (bits 13 to 8) 30 port 1 current ro 2 0000,0000 port 1 current: lsbyte 31 ro 0000,0000 - - port 1 current: msbyte (bits 13 to 8) 32 port 1 voltage ro 2 0000,0000 port 1 voltage: lsbyte 33 ro 0000,0000 - - port 1 voltage: msbyte (bits 13 to 8) 34 port 2 current ro 2 0000,0000 port 2 current: lsbyte 35 ro 0000,0000 - - port 2 current: msbyte (bits 13 to 8) 36 port 2 voltage ro 2 0000,0000 port 2 voltage: lsbyte 37 ro 0000,0000 - - port 2 voltage: msbyte (bits 13 to 8) 38 port 3 current ro 2 0000,0000 port 3 current: lsbyte 39 ro 0000,0000 - - port 3 current: msbyte (bits 13 to 8) 3a port 3 voltage ro 2 0000,0000 port 3 voltage: lsbyte 3b ro 0000,0000 - - port 3 voltage: msbyte (bits 13 to 8) 3c port 4 current ro 2 0000,0000 port 4 current: lsbyte 3d ro 0000,0000 - - port 4 current: msbyte (bits 13 to 8) 3e port 4 voltage ro 2 0000,0000 port 4 voltage: lsbyte 3f ro 0000,0000 - - port 4 voltage: msbyte (bits 13 to 8) 40 poe plus r/w 1 0000,---- poep4 poep3 poep2 poep1 - - - - 41 firmware revision ro 1 rrrr,rrr r firmware revision 42 i 2 c watchdog r/w 1 0001,0110 - - - watchdog disable wds 43 device id r/w 1 111,sr[4:0] device id number silicon revision number 45 cool down/gate drive r/w 1 0000,0000 cldn igate - - - - - 60 port 1 detect resistance ro 2 0000,0000 port 1 resistance: lsbyte 61 ro 0000,0000 rs1 port 1 resistance: msbyte (bits 13 to 8) 62 port 2 detect resistance ro 2 0000,0000 port 2 resistance: lsbyte 63 ro 0000,0000 rs2 port 2 resistance: msbyte (bits 13 to 8) 64 port 3 detect resistance ro 2 0000,0000 port 3 resistance: lsbyte 65 ro 0000,0000 rs3 port 3 resistance: msbyte (bits 13 to 8) 66 port 4 detect resistance ro 2 0000,0000 port 4 resistance: lsbyte 67 ro 0000,0000 rs4 port 4 resistance: msbyte (bits 13 to 8) 68 port 1 detect voltage difference ro 2 0000,0000 port 1 voltage difference (bits 7 to 0) 69 ro 0000,0000 vds1 port 1 voltage difference: msbyte (bits 11 to 8) 6a port 2 detect voltage difference ro 2 0000,0000 port 2 voltage difference (bits 7 to 0) 6b ro 0000,0000 vds2 port 2 voltage difference: msbyte (bits 11 to 8) 6c port 3 detect voltage difference ro 2 0000,0000 port 3 voltage difference (bits 7 to 0) 6d ro 0000,0000 vds3 port 3 voltage difference: msbyte (bits 11 to 8) 6e port 4 detect voltage difference ro 2 0000,0000 port 4 voltage difference (bits 7 to 0) 6f ro 0000,0000 vds4 port 4 voltage difference: msbyte (bits 11 to 8)
49 tps23861 www.ti.com slusbx9e ? march 2014 ? revised march 2016 product folder links: tps23861 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated 7.5.1 interrupt register command = 00h with 1 data byte, read only bits d7 d6 d5 d4 d3 d2 d1 d0 bit name supf strtf ifault clasc detc disf pgc pec reset or por value 1 0 0 0 0 0 0 0 active high, each bit corresponds to a particular event that occurred. each bit can be individually reset by doing a read at the corresponding event register address, or by setting bit 7 of reset register. any active bit of the interrupt register activates the int output if its corresponding enable bit in the interrupt enable register is set, as well as the inten bit in the general mask register. bit descriptions supf: indicates that a supply event fault occurred. supf = tsd || vduv || vpuv 1 = at least one supply event fault occurred. 0 = no such event occurred. strtf: indicates that a start fault occurred on at least one port. strtf = strt1 || strt2 || strt3 || strt4 1 = start fault occurred for at least one port. 0 = no start fault occurred. ifault: indicates that an icut or ilim fault occurred on at least one port. ifault = icut1 || icut2 || icut3 || icut4 || ilim1 || ilim2 || ilim3 || ilim4 1 = icut or ilim fault occurred for at least one port. 0 = no icut or ilim fault occurred. clasc: indicates that at least one classification cycle occurred on at least one port. clasc = clsc1 || clsc2 || clsc3 || clsc4 1 = at least one classification cycle occurred for at least one port. 0 = no classification cycle occurred. detc: indicates that at least one detection cycle occurred on at least one port. detc = detc1 || detc2 || detc3 || detc4 1 = at least one detection cycle occurred for at least one port. 0 = no detection cycle occurred. disf: indicates that a disconnect event occurred on at least one port. disf = disf1 || disf2 || disf3 || disf4 1 = disconnect event occurred for at least one port. 0 = no disconnect event occurred. pgc: indicates that a power good status change occurred on at least one port. pgc = pgc1 || pgc2 || pgc3 || pgc4 1 = power good status change occurred on at least one port. 0 = no power good status change occurred.
50 tps23861 slusbx9e ? march 2014 ? revised march 2016 www.ti.com product folder links: tps23861 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated pec: indicates that a power enable status change occurred on at least one port. pec = pec1 || pec2 || pec3 || pec4 1 = power enable status change occurred on at least one port. 0 = no power enable status change occurred.
51 tps23861 www.ti.com slusbx9e ? march 2014 ? revised march 2016 product folder links: tps23861 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated 7.5.2 interrupt enable register command = 01h with 1 data byte, read/write bits d7 d6 d5 d4 d3 d2 d1 d0 bit name supen strten ifen clcen deen disen pgsen pesen reset or por value 1 a a 0 0 a 0 0 each bit corresponds to a particular event or fault as defined in the interrupt register. writing a 1 into a bit allows the corresponding event to generate an interrupt on the int pin. writing a 0 into a bit masks the corresponding event/fault from activating the int pin. note the bits of the interrupt register always change state according to events or faults, regardless of the state of the interrupt enable register. the inten bit of the general mask 1 register must also be set in order to allow an event to activate the int output. bit descriptions supen: supply event fault enable bit. 1 = supply event fault activates the int output. 0 = supply event fault has no impact on int output. strten: start fault enable bit. 1 = start fault activates the int output. 0 = start fault has no impact on int output. ifen: ifault enable bit. 1 = icut or ilim fault occurrence activates the int output. 0 = icut or ilim fault occurrence has no impact on int output. clcen: classification cycle interrupt enable bit. 1 = classification cycle occurrence activates the int output. 0 = classification cycle occurrence has no impact on int output. deen: detection cycle interrupt enable bit. 1 = detection cycle occurrence activates the int output. 0 = detection cycle occurrence has no impact on int output. disen: disconnect event interrupt enable bit. 1 = disconnect event occurrence activates the int output. 0 = disconnect event occurrence has no impact on int output. pgsen: power good status change interrupt enable bit. 1 = power good status change activates the int output. 0 = power good status change has no impact on int output. pesen: power enable status change interrupt enable bit. 1 = power enable status change activates the int output. 0 = power enable status change has no impact on int output.
52 tps23861 slusbx9e ? march 2014 ? revised march 2016 www.ti.com product folder links: tps23861 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated 7.5.3 power event register command = 02h with 1 data byte, read only command = 03h with 1 data byte, clear on read bits d7 d6 d5 d4 d3 d2 d1 d0 bit name pgc4 pgc3 pgc2 pgc1 pec4 pec3 pec2 pec1 reset or por value 0 0 0 0 0 0 0 0 active high, each bit corresponds to a particular event that occurred. each bit pgcn, pecn represents an individual port. a read at each location (02h or 03h) returns the same register data with the exception that the clear-on-read command clears all bits of the register. if this register is causing the int pin to be activated, this clear-on-read command releases the int pin. any active bit will have an impact on the interrupt register as indicated in the interrupt register description. bit descriptions pgc4-pgc1: indicates that a power good status change occurred. 1 = power good status change occurred. 0 = no power good status change occurred. pec4-pec1: indicates that a power enable status change occurred. 1 = power enable status change occurred. 0 = no power enable status change occurred.
53 tps23861 www.ti.com slusbx9e ? march 2014 ? revised march 2016 product folder links: tps23861 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated 7.5.4 detection event register command = 04h with 1 data byte, read only command = 05h with 1 data byte, clear on read bits d7 d6 d5 d4 d3 d2 d1 d0 bit name clsc4 clsc3 clsc2 clsc1 detc4 detc3 detc2 detc1 reset or por value 0 0 0 0 0 0 0 0 active high, each bit corresponds to a particular event that occurred. each bit clscn, detcn represents an individual port. a read at each location (04h or 05h) returns the same register data with the exception that the clear-on-read command clears all bits of the register. these bits are cleared when port n is turned off. if this register is causing the int pin to be activated, this clear-on-read command releases the int pin. any active bit will have an impact on the interrupt register as indicated in the interrupt register description. bit descriptions clsc4-clsc1: indicates that at least one classification cycle occurred. 1 = at least one classification cycle occurred. 0 = no classification cycle occurred. detc4-detc1: indicates that at least one detection cycle occurred. 1 = at least one detection cycle occurred. 0 = no detection cycle occurred.
54 tps23861 slusbx9e ? march 2014 ? revised march 2016 www.ti.com product folder links: tps23861 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated 7.5.5 fault event register command = 06h with 1 data byte, read only command = 07h with 1 data byte, clear on read bits d7 d6 d5 d4 d3 d2 d1 d0 bit name disf4 disf3 disf2 disf1 icut4 icut3 icut2 icut1 reset or por value 0 0 0 0 0 0 0 0 active high, each bit corresponds to a particular event that occurred. each bit disfn, icutn represents an individual port. a read at each location (06h or 07h) returns the same register data with the exception that the clear-on-read command clears all bits of the register. these bits are cleared by i 2 c power-off command (poffn) or port-reset command (respn). if this register is causing the int pin to be activated, this clear-on-read releases the int pin. any active bit will have an impact on the interrupt register as indicated in the interrupt register description. bit descriptions disf4-disf1: indicates that a disconnect event occurred. 1 = disconnect event occurred. 0 = no disconnect event occurred. icut4-icut1: indicates that an icut fault occurred. 1 = icut fault occurred. 0 = no icut fault occurred.
55 tps23861 www.ti.com slusbx9e ? march 2014 ? revised march 2016 product folder links: tps23861 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated 7.5.6 start/ilim event register command = 08h with 1 data byte, read only command = 09h with 1 data byte, clear on read bits d7 d6 d5 d4 d3 d2 d1 d0 bit name ilim4 ilim3 ilim2 ilim1 strt4 strt3 strt2 strt1 reset or por value 0 0 0 0 0 0 0 0 active high, each bit corresponds to a particular event that occurred. each bit ilimn, strtn represents an individual port. a read at each location (08h or 09h) returns the same register data with the exception that the clear-on-read command clears all bits of the register. these bits are cleared by i 2 c power-off command (poffn) or port-reset command (respn). if this register is causing the int pin to be activated, this clear-on-read command releases the int pin. any active bit has an impact on the interrupt register as indicated in the interrupt register description. bit descriptions strt4-strt1: indicates that a start fault occurred at port turn on. this may be caused by: 1. overcurrent (foldback) condition at the end of t start . 2. detect or classification fault following a pushbutton pwon command. 3. detect fault or classification unknown, mismatch or overcurrent in auto mode. 1 = inrush fault or class/detect error occurred. 0 = no inrush fault or class/detect error occurred. ilim4-ilim1: indicates that an ilim fault occurred, which means the port has limited its output current to ilim or the folded back ilim for more than t lim . 1 = ilim fault occurred. 0 = no ilim fault occurred.
56 tps23861 slusbx9e ? march 2014 ? revised march 2016 www.ti.com product folder links: tps23861 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated 7.5.7 supply event register command = 0ah with 1 data byte, read only command = 0bh with 1 data byte, clear on read bits d7 d6 d5 d4 d3 d2 d1 d0 bit name tsd - vduv vpuv - - - - por value 0 0 1 1 0 0 0 0 active high, each bit corresponds to a particular event that occurred. a read at each location (0ah or 0bh) returns the same register data with the exception that the clear-on-read command clears all bits of the register. if this register is causing the int pin to be activated, this clear-on-read releases the int pin. any active bit has an impact on interrupt register as indicated in the interrupt register description. bit descriptions tsd: indicates that a thermal shutdown occurred. when there is thermal shutdown, all ports are powered off and are put in off mode. the tps23861 internal circuitry continues to operate however, including the a/d converters. note that at as soon as the internal temperature has decreased below the low threshold, the ports can be powered on regardless of the status of the tsd bit. 1 = thermal shutdown occurred. 0 = no thermal shutdown occurred. vduv: indicates that a vdd uvlo occurred. vduv is set following a power-on reset or if the voltage at the vdd pin falls below v uvdd_f 1 = vdd uvlo occurred. 0 = no vdd uvlo occurred. vpuv: indicates that a vpwr uvlo occurred. vpuv is set following a power-on reset or if the voltage at the vpwr pin falls below v puv_f . 1 = vpwr undervoltage occurred. 0 = no vpwr undervoltage occurred. note if the reset input is pulled low during normal operation, vpuv is set if vpwr is below its uvlo threshold. there is no impact on vduv since vdd is maintained. when vpwr drops below v puv_f but not as low as v uvlopw_f all ports are powered off as if a push-button off was executed. (same as writing 1 to poffn in power enable register.) when vpwr undervoltage (below v uvlopw_f ) occurs, all ports are powered off, and there is a power-on reset.
57 tps23861 www.ti.com slusbx9e ? march 2014 ? revised march 2016 product folder links: tps23861 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated 7.5.8 port n status register 7.5.8.1 port 1 status register command = 0ch with 1 data byte, read only bits d7 d6 d5 d4 d3 d2 d1 d0 bit name class p1 detect p1 reset or por value 0 0 0 0 0 0 0 0 7.5.8.2 port 2 status register command = 0dh with 1 data byte, read only bits d7 d6 d5 d4 d3 d2 d1 d0 bit name class p2 detect p2 reset or por value 0 0 0 0 0 0 0 0 7.5.8.3 port 3 status register command = 0eh with 1 data byte, read only bits d7 d6 d5 d4 d3 d2 d1 d0 bit name class p3 detect p3 reset or por value 0 0 0 0 0 0 0 0 7.5.8.4 port 4 status register command = 0fh with 1 data byte, read only bits d7 d6 d5 d4 d3 d2 d1 d0 bit name class p4 detect p4 reset or por value 0 0 0 0 0 0 0 0 represents the most recent classification and detection results for port n. these bits are cleared when port n is turned off. note in order to disable detection for any port with unknown, short circuit, open circuit, or mosfet fault detection status (0x0c-0x0f), clear the corresponding port detex bits in 0x14 instead of writing the port off command to 0x12, 0x19, or 0x1a.
58 tps23861 slusbx9e ? march 2014 ? revised march 2016 www.ti.com product folder links: tps23861 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated bit descriptions class pn[3:0]: class pn is a 4-bit field for each port. the value of class pn is the most recent classification result on port n. the selection is as following: class pn classification status 0000 unknown 0001 class 1 0010 class 2 0011 class 3 0100 class 4 0101 reserved ? read as class 0 0110 class 0 0111 overcurrent 1000 class mismatch a class mismatch can occur only during two-event classification. if the classification status for the first and second event are different, and the second classification status is not overcurrent , the classification status is set to class mismatch. if the status of the first classification event is ? overcurrent ? , the classification status will be set to ? overcurrent ? in the class pn, and there will be no second classification event in any case. in auto mode, port will not power on automatically, but still can be powered on through the power enable register. the appropriate strtn bit is set in the start/ilim event register following these sorts of faults during classification. detect pn[3:0]: detect pn is a 4-bit field for each port. the value of detect pn is the most recent detection result on port n. note bit states 1001 ? 1100 apply to legacy detection only. the selection is as following: detect pn detect status 0000 unknown (por value) 0001 short circuit ( < 500 ) 0010 reserved 0011 resistance too low 0100 resistance valid 0101 resistance too high 0110 open circuit 0111 reserved 1000 mosfet fault 1001 legacy detect 1010 capacitance measurement invalid: detect measurement beyond clamp voltage 1011 capacitance measurement invalid: insufficient v measured 1100 capacitance measurement is valid, but outside the range of a legacy device.
59 tps23861 www.ti.com slusbx9e ? march 2014 ? revised march 2016 product folder links: tps23861 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated 7.5.9 power status register command = 10h with 1 data byte, read only bits d7 d6 d5 d4 d3 d2 d1 d0 bit name pg4 pg3 pg2 pg1 pe4 pe3 pe2 pe1 reset or por value 0 0 0 0 0 0 0 0 each bit represents the actual power status of a port. each bit pgn, pen represents an individual port. these bits are cleared when port n is turned off, including if the turn off is caused by a fault condition. bit descriptions pg4-pg1: each bit, when at 1, indicates that the port is on and that the voltage at drainn has gone below vpgt while the port is powered on. these bits are latched high once the turn on is complete and can only be cleared when the port is turned off or following a reset or power-on reset. 1 = power is good. 0 = power is not good. pe4-pe1: each bit indicates the on/off state of the corresponding port. 1 = port is on. 0 = port is off. 7.5.10 i 2 c slave address register command = 11h with 1 data byte, read only bits d7 d6 d5 d4 d3 d2 d1 d0 bit name auto sla6 sla5 sla4 sla3 sla2 sla1 sla0 initial eeprom value 1 0 1 0 0 0 0 0 bit descriptions sla6-sla0: i 2 c device address, stored in eeprom . this address can be changed by following the i 2 c slave address programming protocol. for more details, see the i 2 c slave address and auto bit programming . note the programmed device address should not be any of 0x00, 0x30, 0x0c. auto: defines whether the controller operates automatically in auto mode even in the absence of a host controller. automatic operation is described in independent operation when the bit is set section. the state of this bit is monitored only immediately following a power-on reset or after the reset input has been activated. the impact of that bit state on registers after reset is reflected in table 10 and is referred to ? a ? . description binary device address 6 5 4 3 2 1 0 broadcast access 0 1 1 0 0 0 0 alert response 0 0 0 1 1 0 0 slave number sla6 sla5 sla4 a3 pin sla2 sla1 sla0
60 tps23861 slusbx9e ? march 2014 ? revised march 2016 www.ti.com product folder links: tps23861 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated 7.5.11 operating mode register command = 12h with 1 data byte, r/w bits d7 d6 d5 d4 d3 d2 d1 d0 bit name port 4 mode port 3 mode port 2 mode port 1 mode reset or por value aa aa aa aa each field configures the operating mode per port. note an operating mode write command to 0x12 with a transition from off mode to auto mode or from off mode to semi-auto mode requires an i 2 c bus processing delay of 1.2 ms when followed by a detect/class enable (0x14) write command. this delay applies from the end of the operating mode command (stop pulse) to the end of the detect/class enable command (stop pulse). bit descriptions port n mode[1:0]: the selection is as following: port n mode [1:0] operating mode 00 off 01 manual 10 semi-auto 11 auto in off mode, the port is off and there is neither detection nor classification. in manual mode, there is no automatic state change. in semi-auto mode, detection and classification are automated but not the port power on, while in auto mode all three are automated. see device functional modes for a detailed description of each of the four operating modes. note for any port with power enable set (pex=1 in 0x10), ensure that port power good status in 0x10 is also set (pgx=1) prior to changing the mode to off in the operating mode register (0x12). 7.5.12 disconnect enable register command = 13h with 1 data byte, r/w bits d7 d6 d5 d4 d3 d2 d1 d0 bit name - - - - dcde4 dcde3 dcde2 dcde1 reset or por value - - - - a a a a enables the disconnect detection mechanism for each port. bit descriptions dcde4-dcde1: dc disconnect enable for each port. disconnect consists of measuring the port current at senn pin, starting the tdis timer if this current is below a threshold and turning the port off if a time out occurs. also, the corresponding disconnect bit (disfn) in the fault event register is set accordingly. the tdis timer is reset each time the current goes higher than the disconnect threshold for 13% of t mpdo . the counter does not decrement below zero. look at the timing configuration register for more details on how to set t mpdo by writing to the tdis field.
61 tps23861 www.ti.com slusbx9e ? march 2014 ? revised march 2016 product folder links: tps23861 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated 7.5.13 detect/class enable register command = 14h with 1 data byte, r/w bits d7 d6 d5 d4 d3 d2 d1 d0 bit name cle4 cle3 cle2 cle1 dete4 dete3 dete2 dete1 reset or por value a a a a a a a a detection and classification enable for each port. when in manual mode, setting a bit means that only one cycle (detection or classification) is performed for the corresponding port. the bit is automatically cleared when the cycle has been completed. note the same result can be obtained by writing to the detect/class restart register. note write commands to either 0x12, 0x18, 0x19, or 0x1a require an i 2 c bus processing delay of 1.2 ms when followed by a detect/class enable (0x14) write command. this delay applies from the end of the 0x12, 0x18, 0x19, or 0x1a command (stop pulse) to the end of the detect/class enable command (stop pulse). it is also cleared if a port turn off (power enable register) is issued. in semi-auto mode, while the port is not powered up, detection and classification are performed continuously, as long as the clen and deten bits are kept set. first, detection is performed. if a resistance valid status is returned, classification follows. after, the detect-class sequence repeats. if a valid status is not returned by the detection event, classification is skipped, and detection is repeated. in auto mode, if the port is not powered up and the deten and clen bits are set, classification follows a valid detect, and power-on follows classification unless classification returns unknown, overcurrent or class mismatch status. during the cool-down cycle following a start, icut or ilim, any detect/class enable command for that port are delayed until the end of the cool-down period. note at the end of the cool-down period, one or more detection/class cycles are automatically restarted as described previously if the detect enable bit is set. bit descriptions cle4-cle1: classification enable bits. 1 = enabled. 0 = disabled. dete4-dete1: detection enable bits. 1 = enabled. 0 = disabled.
62 tps23861 slusbx9e ? march 2014 ? revised march 2016 www.ti.com product folder links: tps23861 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated 7.5.14 port power priority register command = 15h with 1 data byte, r/w bits d7 d6 d5 d4 d3 d2 d1 d0 bit name fse4 fse3 fse2 fse1 r15[3] r15[2] r15[1] r15[0] reset or por value a a a a 0 0 0 0 bit descriptions fse4-fse1: port power priority bits to support fast shutdown; one bit per port. it is used to specify which port or ports is/are shut down in response to an external assertion of the shtdwn pin fast shutdown signal. the turn- off procedure is similar to a port reset using reset command (reset register). if one of these bits is set while the shtdwn pin is low, that port is shut down as well. 1 = when the shtdwn is forced to a low level, the corresponding port is powered off. 0 = shtdwn signal has no impact on the port. reserved: bits r15[3:0] are reserved for future use. undesirable behavior may result if the value of these bits are changed from their reset value.
63 tps23861 www.ti.com slusbx9e ? march 2014 ? revised march 2016 product folder links: tps23861 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated 7.5.15 timing configuration register command = 16h with 1 data byte, r/w bits d7 d6 d5 d4 d3 d2 d1 d0 bit name tlim tstart ticut tdis reset or por value 0 0 0 0 0 0 0 0 these bits define the timing configuration for all four ports. note the pgn and pen bits in the power status register are cleared when there is a start, icut or ilim condition. bit descriptions tlim[1:0]: ilim fault timing, which is the foldback current limit time duration before port turn off. this timer is loaded with its maximum count corresponding to t lim after expiration of the t start period; the timer counts down when the port is limiting its output current to ilim. if the ilim timer counts down to zero, the port is powered off. after the port is powered off the cool-down period commences. the cool-down period is selected by the cldn field in the cool down/gate drive register. during the cool-down period the port will not engage in detection, classification, or powered-up operation. when the port is powered up and while the port current is below ilim, the same counter increments at a rate 1/16 th of the count-down rate (independent of the setting in the cldn field). the counter does not increment past the maximum count corresponding to the programmed tlim value. note at the end of the cool-down period, when in semi-auto or auto mode, a detection cycle is automatically restarted if the detect enable bit is set. when a poepn bit in the poe plus register is cleared, the t lim used for the associated port is always the nominal value (~60 ms). if the poepn bit is set, then t lim for associated port is programmable with the following selection: tlim[1:0] nominal t lim (ms) when poepn bit is set 00 60 01 30 10 15 11 10 tstart[1:0]: this 2-bit field sets the length of the t start period, which is the maximum allowed overcurrent time during inrush. if at the end of the t start period the current is still limited to i inrush , the port is powered off. this is followed by a cool-down period, set with the cldn field in the cool down/gate drive register, during which the port cannot be turned on if in semi-auto or auto mode. note at the end of cool-down cycle, when in semi-auto or auto mode, a detection cycle is automatically restarted if the class and detect enable bits are set.
64 tps23861 slusbx9e ? march 2014 ? revised march 2016 www.ti.com product folder links: tps23861 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated the selection is as following: tstart [1:0] nominal t start (ms) 00 60 01 30 10 120 11 reserved ticut[1:0]: icut fault timing, which is the overcurrent time duration before port turn off (t ovld ). this timer is loaded with its maximum count corresponding to t ovld after expiration of the t start period; the timer counts down when the port current exceeds icut. if the icut timer counts down to zero, the port is powered off. after the port is powered off the cool-down period commences. the cool-down period is set with the cldn field in the cool down/gate drive register. during the cool-down period the port will not engage in detection, classification, or powered-up operation. when the port is powered up and while the port current is below icut, the same counter increments at a rate 1/16 th of the count-down rate (independent of the setting in the cldn field). the counter does not increment past the maximum count corresponding to the programmed ticut value. note at the end of cool-down cycle, when in semi-auto or auto mode, a detection cycle is automatically restarted if the detect enable bit is set. the selection is as following: ticut[1:0] nominal t ovld (ms) 00 60 01 30 10 120 11 240 tdis[1:0]: disconnect delay, which is the time to turn off a port once there is a disconnect condition. after port power on and the completion of the t start period the tdis counter is started when the port current drops below the disconnect threshold established in the dcthn fields, and the counter is reset each time the current goes continuously higher than the disconnect threshold for 13% of t mpdo . the counter does not decrement below zero. the selection is as following: tdis[1:0] nominal t mpdo (ms) 0 0 360 0 1 90 1 0 180 1 1 720
65 tps23861 www.ti.com slusbx9e ? march 2014 ? revised march 2016 product folder links: tps23861 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated 7.5.16 general mask 1 register command = 17h with 1 data byte, read/write bits d7 d6 d5 d4 d3 d2 d1 d0 bit name inten mains r17[3] r17[2] r17[1] m250 reset or por value 1 0 0 0 reserved reserved reserved 0 bit descriptions inten: int pin enable bit. writing a 1 permits any bit of the interrupt register to activate the int output. note activating inten has no impact on the event registers. 1 = any enabled bit of the interrupt register can activate the int output. 0 = int output cannot be activated. reserved: bits r17[3], r17[2] and r17[1] are reserved for future use. undesirable behavior may result if the value of these bits are changed from the reset value. mains: detection voltage measurement duration bit. set or clear this bit to correspond to the mains frequency local to where the tps23861 is being used in a system. the a/d converter will perform 16 conversions during the detection cycle. the results of these 16 conversions are averaged resulting in a total acquisition time equal to one cycle of the mains frequency. this technique greatly reduces mains-induced interference in the detection cycle measurement. 1 = convert port voltage during detection at a rate of 960 a/d conversions per second. this corresponds to 16 conversions during one period of 60-hz mains frequency. 0 = convert port voltage during detection at a rate of 800 a/d conversions per second. this corresponds to 16 conversions during one period of 50-hz mains frequency. m250: current-sense-resistor-selection bit. setting this bit directs the tps23861 to use icut and classification look-up tables corresponding to a 250-m current-sense resistor. 1 = set this bit if a 250-m current-sense resistor is used as a current-sense resistor. 0 = clear this bit if a 255-m current-sense resistor is used as a current-sense resistor.
66 tps23861 slusbx9e ? march 2014 ? revised march 2016 www.ti.com product folder links: tps23861 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated 7.5.17 detect/class restart register command = 18h with 1 data byte, write only bits d7 d6 d5 d4 d3 d2 d1 d0 bit name rcl4 rcl3 rcl2 rcl1 rdet4 rdet3 rdet2 rdet1 push button register. each bit corresponds to a particular cycle (detect or class restart) per port. each cycle can be individually triggered by writing a ? 1 ? at that bit location, while writing a ? 0 ? does not change anything for that event. in manual mode, a single cycle (detect or class restart) is initiated. in semi-auto and auto mode, the corresponding bit in the detect/class enable register is set, and the tps23861 operates as prescribed in device functional modes section. during the cool-down cycle following a start, icut or ilim, any detect/class restart command for that port is accepted, but the corresponding action is delayed until end of cool-down period. note a detect/class restart write command to 0x18 requires an i 2 c bus processing delay of 1.2 ms when followed by a detect/class enable (0x14) write command. this delay applies from the end of the detect/class restart command (stop pulse) to the end of the detect/class enable command (stop pulse). bit descriptions rcl4-rcl1: restart classification bits. rdet4-rdet1: restart detection bits.
67 tps23861 www.ti.com slusbx9e ? march 2014 ? revised march 2016 product folder links: tps23861 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated 7.5.18 power enable register command = 19h with 1 data byte, write only bits d7 d6 d5 d4 d3 d2 d1 d0 bit name poff4 poff3 poff2 poff1 pwon4 pwon3 pwon2 pwon1 push button register. setting a bit in this register directs the tps23861 to turn a port on or off. used to force a port(s) power on or power off in any mode except off mode or during a port shutdown condition via the shtdwn pin. note a power off write command to 0x19 requires an i 2 c bus processing delay of 1.2 ms when followed by a detect/class enable (0x14) write command. this delay applies from the end of the power off command (stop pulse) to the end of the detect/class enable command (stop pulse). note in semi-auto or in auto mode, as long as the port is kept off, detection and classification are performed continuously if the corresponding class and detect enable bits are set. the details of a power-on operation depends on the operating mode. see device functional modes section for details. writing a ? 1 ? at poffn location powers off the associated port. note writing a ? 1 ? at poffn and pwonn of same port during the same write operation powers off the port. during the cool-down cycle following a start, icut or ilim, when in semi-auto or auto mode, any port turn on using power enable command is ignored. the port can be turned on at the end of the cool-down cycle. when in manual mode, the port powers on immediately in response to a power on command even when in cool-down. bit descriptions poff4-poff1: port power off bits. when poffn is written, the following takes place: ? the corresponding port n voltage registers are cleared. ? the corresponding port n detect resistance register are cleared. ? the clscn and the detcn bits in the detection event register are cleared. ? the corresponding port n status register are cleared. ? the clen and the deten bits in the detect/class enable register are cleared. ? the disfn and icutn bits in the fault event register are cleared. ? the ilimn and the strtn bits in the start/ilim event register are cleared. ? if the port was powered on when poffn is set, the port is powered off, and the following occurs. ? the pgcn and the pecn bits in the power event register are set. ? the pgn and pen bits in the power status register are cleared. pwon4-pwon1: port power on bits. note for any port with power enable set (pex=1 in 0x10), ensure that port power good status in 0x10 is also set (pgx=1) prior to writing a power off command to the power enable register (0x19).
68 tps23861 slusbx9e ? march 2014 ? revised march 2016 www.ti.com product folder links: tps23861 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated 7.5.19 reset register command = 1ah with 1 data byte, write only bits d7 d6 d5 d4 d3 d2 d1 d0 bit name clrain clinp resal resp4 resp3 resp2 resp1 push button register. writing a ? 1 ? at a bit location triggers an event while a ? 0 ? has no impact. note a reset port write command to 0x1a requires an i 2 c bus processing delay of 1.2 ms when followed by a detect/class enable (0x14) write command. this delay applies from the end of the reset port command (stop pulse) to the end of the detect/class enable command (stop pulse). bit descriptions clrain: clear all interrupts bit. writing a ? 1 ? to clrain clears all event registers and all bits in the interrupt register. it also releases the int pin. clinp: when a ? 1 ? is written to this register, the tps23861 releases the int pin without any impact on either the event registers nor on the interrupt register. resal: reset register bits when a ? 1 ? is written to this location. writing a ? 1 ? to this location results in a state equivalent to a power-up reset. note for any port with power enable set (pex=1 in 0x10), ensure that port power good status in 0x10 is also set (pgx=1) prior to writing a reset port command to the reset register (0x1a). note the vduv and vpuv bits (supply event register) follow the state of vdd and vpwr supply rails. resp4-resp1: reset port bits. used to force an immediate port(s) turn off in any mode, by writing a ? 1 ? at the corresponding respn bit location(s). when port n is reset, the following takes place. ? the corresponding port n voltage register are cleared. ? the clcsn and the detcn bits in the detection event register are cleared. ? the corresponding port n status register are cleared. ? the clen and the deten bits in the detect/class enable register are cleared. ? the disfn and icutn bits in the fault event register are cleared. ? the ilimn and strtn bits in the start/ilim event register are cleared. ? if in cool-down, the lockout functionality of the cool-down timer is cancelled. ? if the port was powered on when respn is set, the port is shut off, and the following occurs. ? the pgcn and the pecn bits in the power event register are set. ? the pgn and pen bits in the power status register are cleared.
69 tps23861 www.ti.com slusbx9e ? march 2014 ? revised march 2016 product folder links: tps23861 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated 7.5.20 legacy detect mode register command = 20h with 1 data byte, read/write bits d7 d6 d5 d4 d3 d2 d1 d0 bit name legmod4 legmod3 legmod2 legmod1 reset or por value 00 00 00 00 legacy-detect operation is described in legacy device detection . the tps23861 can perform a legacy-detect operation only or a standard detection followed by a legacy-detect operation when directed by the rdetn push- button command in the detect/class restart register, or in semi-auto or auto mode when the deten bit in the detect/class enable register is set. note that in semi-auto or in auto mode, the port will not automatically power up if a legacy device is detected. in these cases, the port must be powered on by the host. bit descriptions legmodn[1:0]: legacy-detection-mode field. this field defines the legacy-detect mode of port n as follows. legmodn[1:0] legacy detect mode 00 legacy detect disabled; if deten bit in detect/class enable register is set, a standard (resistance only) detection sequence will be performed. 01 legacy detect sequence only; if deten bit in detect/class enable register is set, a legacy detect sequence will be performed 10 standard + legacy detect sequence; if deten bit in detect/class enable register is set, a standard detection followed by legacy detect sequence will be performed 11 reserved 7.5.21 two-event classification register command = 21h with 1 data byte, read/write bits d7 d6 d5 d4 d3 d2 d1 d0 bit name teclen4 teclen3 teclen2 teclen1 reset or por value 0a 0a 0a 0a the two-event classification register controls whether a second physical-layer classification event occurs after a class 4 pd is classified under the following circumstances: ? in manual mode, when clen is set or a pushbutton rcln bit is written. ? in semi-auto mode, when a pwonn pushbutton command is written. ? in auto mode. bit descriptions teclenn[1:0]: the teclenn field sets the conditions for pse-initiated two-event physical layer classification as follows. the details of these conditions depend on the operating mode as outlined in the preceding paragraph and the device functional modes section. table 11. teclenn field encoding teclenn[1:0] conditions for two-event physical-layer classification 00 two-event physical-layer classification is disabled 01 a second classification event is initiated if a class 4 classification event occurs 10 reserved 11 a second classification event is initiated if a class 4 classification event occurs
70 tps23861 slusbx9e ? march 2014 ? revised march 2016 www.ti.com product folder links: tps23861 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated 7.5.22 interrupt timer register command = 27h with 1 data byte, read/write bits d7 d6 d5 d4 d3 d2 d1 d0 bit name r27[7] r27[6] r27[5] r27[4] tmr[3] tmr[2] tmr[1] tmr[0] reset or por value 0 0 0 0 0 0 0 0 bit descriptions tmr[3:0]: non-critical interrupts may be deferred using an internal timer. once loaded with a non-zero value, the internal timer counts continuously with period calculated as follows: where ? t = timer period, ms ? n = 4-bit value in tmr[3:0] field ? t step = 10 ms (1) non-critical interrupts generated within the tps23861 will be passed to the interrupt-handling hardware whenever the timer counts down to 0. (the timer then reloads and continues to count.) note ? interrupt-handling hardware ? includes all interrupt-enabling functionality as well. critical and non-critical interrupts are defined in table 6 . when the tmr[3:0] field is read, the contents will be the contents last written by firmware. when tmr[3:0] = 0 all interrupts will be handled as they are generated. in other words, this function is disabled when tmr[3:0] = 0000. reserved: bits r27[7:4] are reserved for future use. undesirable behavior may result if the value of these bits are changed from the reset value. step t n t u
71 tps23861 www.ti.com slusbx9e ? march 2014 ? revised march 2016 product folder links: tps23861 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated 7.5.23 disconnect threshold register command = 29h with 1 data byte, read/write bits d7 d6 d5 d4 d3 d2 d1 d0 bit name dcth4 dcth3 dcth2 dcth1 reset or por value 00 00 00 00 disconnect current thresholds may be programmed individually for each port. 7.5.23.1 bits description dcthn[1:0]: a 2-bit field used to set the current threshold for disconnect. if the port is powered on and the current goes below the disconnect threshold set by dcthn, the tdis counter is started. if the tdis timer times out the port is powered down. dcthn field disconnect threshold, ma 00 7.5 01 15 10 30 11 50
72 tps23861 slusbx9e ? march 2014 ? revised march 2016 www.ti.com product folder links: tps23861 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated 7.5.24 icutnm config register 7.5.24.1 icut21 config register command = 2ah with 1 data byte, read/write bits d7 d6 d5 d4 d3 d2 d1 d0 bit name icut port 2 icut port 1 reset or por value 0 0 0 0 0 0 0 0 7.5.24.2 icut43 config register command = 2bh with 1 data byte, read/write bits d7 d6 d5 d4 d3 d2 d1 d0 bit name icut port 4 icut port 3 reset or por value 0 0 0 0 0 0 0 0 (1) poepn bit should be set according to icut value for host to ensure the icut and ilim relationship. 7.5.24.3 bits description icut port n[2:0]: is a 3-bit field used to set the icut current threshold. if the current threshold set by icut port n is exceeded, the ticut timer begins to count. when the terminal count (0) is reached, an icut fault is declared, and the port is shut down. note the current values in the following table are nominal values. icut port n field i cut (ma) poepn (1) 000 374 0 001 110 0 010 204 0 011 374 0 100 754 1 101 592 1 110 645 1 111 920 1
73 tps23861 www.ti.com slusbx9e ? march 2014 ? revised march 2016 product folder links: tps23861 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated 7.5.25 temperature register command = 2ch with 1 data byte, read only bits d7 d6 d5 d4 d3 d2 d1 d0 bit name temp[7:0] reset or por value 0 0 0 0 0 0 0 0 die temperature register. bit descriptions temp[7:0]: 8-bit data conversion result of temperature. the equation defining the temperature measured is: where ? t = temperature, c ? tstep = lsb value ? n = 8-bit value in temp[7:0] (2) mode full scale value lsb value any 150 c (typical) 0.7 c note temperature sensor performance is only typical, not production tested and not ensured. step t 20 n t u
74 tps23861 slusbx9e ? march 2014 ? revised march 2016 www.ti.com product folder links: tps23861 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated 7.5.26 input voltage register command = 2eh with 2 data byte (lsbyte first, msbyte second), read only lsb: 2eh bits d7 d6 d5 d4 d3 d2 d1 d0 bit name input voltage[7:0] reset or por value 0 0 0 0 0 0 0 0 msb: 2fh bits d7 d6 d5 d4 d3 d2 d1 d0 bit name input voltage[13:8] reset or por value 0 0 0 0 0 0 0 0 bit descriptions data conversion result. the i 2 c data transmission is a 2-byte transfer. input voltage[13:0]: 14-bit data conversion result of input voltage. the update rate is approximately 1 per second. the equation defining the voltage measured is: where ? v = input voltage, v ? n = 14 bit value in input voltage register ? v step = lsb value (3) mode full scale value lsb value any 60 v 3.662 mv note the measurement is made between vpwr and agnd. step v n v u
75 tps23861 www.ti.com slusbx9e ? march 2014 ? revised march 2016 product folder links: tps23861 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated 7.5.27 port n current register 7.5.27.1 port 1 current register command = 30h with 2 data byte (lsbyte first, msbyte second), read only lsb: 30h bits d7 d6 d5 d4 d3 d2 d1 d0 bit name port 1 current[7:0] reset or por value 0 0 0 0 0 0 0 0 msb: 31h bits d7 d6 d5 d4 d3 d2 d1 d0 bit name port 1 current[13:8] reset or por value 0 0 0 0 0 0 0 0 7.5.27.2 port 2 current register command = 34h with 2 data byte (lsbyte first, msbyte second), read only lsb: 34h bits d7 d6 d5 d4 d3 d2 d1 d0 bit name port 2 current[7:0] reset or por value 0 0 0 0 0 0 0 0 msb: 35h bits d7 d6 d5 d4 d3 d2 d1 d0 bit name - - port 2 current[13:8] reset or por value 0 0 0 0 0 0 0 0 7.5.27.3 port 3 current register command = 38h with 2 data byte (lsbyte first, msbyte second), read only lsb: 38h bits d7 d6 d5 d4 d3 d2 d1 d0 bit name port 3 current[7:0] reset or por value 0 0 0 0 0 0 0 0 msb: 39h bits d7 d6 d5 d4 d3 d2 d1 d0 bit name port 3 current[13:8] reset or por value 0 0 0 0 0 0 0 0
76 tps23861 slusbx9e ? march 2014 ? revised march 2016 www.ti.com product folder links: tps23861 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated 7.5.27.4 port 4 current register command = 3ch with 2 data byte (lsbyte first, msbyte second), read only lsb: 3ch bits d7 d6 d5 d4 d3 d2 d1 d0 bit name port 4 current[7:0] reset or por value 0 0 0 0 0 0 0 0 msb: 3dh bits d7 d6 d5 d4 d3 d2 d1 d0 bit name port 4 current[13:8] reset or por value 0 0 0 0 0 0 0 0 port current is monitored continuously when: ? the port is powered on. ? the port is in off mode. data conversion result. the i 2 c data transmission is a 2-byte transfer. note the conversion is done using a ti-proprietary multi-slope integrating converter. bit descriptions port n current[13:0]: 14-bit data conversion result of current for port n. the result depends on whether the current-sense resistor is 250 m or 255 m . the equation defining the current measured is: where ? i = port n current, a ? n = 14-bit value in port n current register ? i step = lsb value (4) r s = 255 m r sense = 250 m full scale lsb value full scale lsb value 1 a 61.039 a 1.02 a 62.260 a step i n i u
77 tps23861 www.ti.com slusbx9e ? march 2014 ? revised march 2016 product folder links: tps23861 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated 7.5.28 port n voltage register 7.5.28.1 port 1 voltage register command = 32h with 2 data byte (lsbyte first, msbyte second), read only lsb: 32h bits d7 d6 d5 d4 d3 d2 d1 d0 bit name port 1 voltage[7:0] reset or por value 0 0 0 0 0 0 0 0 msb: 33h bits d7 d6 d5 d4 d3 d2 d1 d0 bit name port 1 voltage[13:8] reset or por value 0 0 0 0 0 0 0 0 7.5.28.2 port 2 voltage register command = 36h with 2 data byte (lsbyte first, msbyte second), read only lsb: 36h bits d7 d6 d5 d4 d3 d2 d1 d0 bit name port 2 voltage[7:0] reset or por value 0 0 0 0 0 0 0 0 msb: 37h bits d7 d6 d5 d4 d3 d2 d1 d0 bit name port 2 voltage[13:8] reset or por value 0 0 0 0 0 0 0 0 7.5.28.3 port 3 voltage register command = 3ah with 2 data byte (lsbyte first, msbyte second), read only lsb: 3ah bits d7 d6 d5 d4 d3 d2 d1 d0 bit name port 3 voltage[7:0] reset or por value 0 0 0 0 0 0 0 0 msb: 3bh bits d7 d6 d5 d4 d3 d2 d1 d0 bit name port 3 voltage[13:8] reset or por value 0 0 0 0 0 0 0 0
78 tps23861 slusbx9e ? march 2014 ? revised march 2016 www.ti.com product folder links: tps23861 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated 7.5.28.4 port 4 voltage register command = 3eh with 2 data byte (lsbyte first, msbyte second), read only lsb: 3eh bits d7 d6 d5 d4 d3 d2 d1 d0 bit name port 4 voltage[7:0] reset or por value 0 0 0 0 0 0 0 0 msb: 3fh bits d7 d6 d5 d4 d3 d2 d1 d0 bit name port 4 voltage[13:8] reset or por value 0 0 0 0 0 0 0 0 port voltage is monitored continuously when ? the port is powered on. ? the port is in off mode. data conversion result. the i 2 c data transmission is a 2-byte transfer. bit descriptions port n voltage[13:0]: 14-bit data conversion result of voltage for port n. the equation defining the voltage measured is: where ? v = port n voltage, v ? n = 14-bit value in port n voltage register ? v step = lsb value (5) full scale value lsb value 60 v 3.662 mv note the port voltage measurement is made between vpwr and drainn. step v n v u
79 tps23861 www.ti.com slusbx9e ? march 2014 ? revised march 2016 product folder links: tps23861 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated 7.5.29 poe plus register command = 40h with 1 data byte, r/w bits d7 d6 d5 d4 d3 d2 d1 d0 bit name poep4 poep3 poep2 poep1 reset or por value 0 0 0 0 the poepn bit can be set or cleared by the host processor over the i 2 c interface. additionally, the bit is set when in auto mode before the port is powered on following the recognition of a valid class 4 pd. likewise, the poepn bit is cleared before the port is powered on when in auto mode and a class 0, 1, 2 or 3 pd is recognized. one poepn bit supports each port. when the poepn bit for a port is set: ? 2 x i lim foldback curve is applied to a port when the port is powered on. see figure 58 . ? the short-circuit protection threshold (i lim ) for the fet is increased by a factor of 2.5 with respect to the poepn-bit-cleared value. ? the t lim value is selectable via the tlim timer field in the timing configuration register. likewise, when the poepn bit for a port is cleared: ? 1 x i lim foldback curve is applied to a port when the port is powered on. see figure 58 . ? the short-circuit protection threshold (i lim ) for the fet is reduced to a value of 40% of the poepn-bit-set value. ? the t lim value is set to 60 ms. the inrush-foldback behavior is not affected by the setting of the poepn bit. see figure 57 . bit descriptions poepn: poe+ bits. setting this bit causes the 2 x i lim foldback curve to be applied to port n. 1 = use 2 x i lim foldback curve on port n. 0 = use 1 x i lim foldback curve on port n. note poepn bit should be set according to icut value for host to ensure the icut and ilim relationship. see table 15 7.5.30 firmware revision register command = 41h with 1 data byte, read only bits d7 d6 d5 d4 d3 d2 d1 d0 bit name frv reset or por value r r r r r rrr bit descriptions frv[2:0]: firmware revision number.
80 tps23861 slusbx9e ? march 2014 ? revised march 2016 www.ti.com product folder links: tps23861 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated 7.5.31 i 2 c watchdog register command = 42h with 1 data byte, r/w bits d7 d6 d5 d4 d3 d2 d1 d0 bit name iwd[3:0] wds reset or por value 1 0 1 1 0 the i 2 c watchdog timer monitors the i 2 c clock line in order to prevent hung software situations that could leave ports in a hazardous state. the timer can be reset by either edge on scl input. if the watchdog timer times out, the wds bit is set. depending on the value of iwd, all ports may be powered down. the nominal watchdog time- out period is 2 seconds. when the ports are powered down due to a watchdog event, the corresponding bits are cleared in the detection event register (clscn, detn), fault event register (disfn, icutn), start/ilim event register (strtn), port n status registers (class pn, detect pn) and detect/class enable register (clen, deten). the corresponding pen and pgn bits of the power status register are also updated accordingly. bit descriptions iwd3 - iwd0: i 2 c watchdog disable. when equal to 1011, the watchdog is masked. otherwise, it is umasked and the watchdog is operational. wds: i 2 c watchdog timer status, valid even if the watchdog is masked. when set, it means that the watchdog timer has expired without any activity on i 2 c clock line. writing 0 at wds location clears it. note when the watchdog timer expires and if the watchdog is unmasked, all ports are also turned off. when the ports are turned off due to i 2 c watchdog, the corresponding bits in detection event register (clscn, detcn), fault event register (disfn, icutn), start event register (strtn), port n status register (class pn, detect pn), detect/class enable register (clen, deten) and power-on fault register (pfn) are also cleared. the corresponding pgcn and pecn bits of power event register is set if there is a change. the corresponding pen and pgn bits of power status register are updated accordingly 7.5.32 device id register command = 43h with 1 data byte, r/w bits d7 d6 d5 d4 d3 d2 d1 d0 bit name did sr reset or por value 1 1 1 sr[4:0] bit descriptions did: device id number (111). sr: silicon revision number.
81 tps23861 www.ti.com slusbx9e ? march 2014 ? revised march 2016 product folder links: tps23861 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated 7.5.33 cool down/gate drive register command = 45h with 1 data byte, r/w bits d7 d6 d5 d4 d3 d2 d1 d0 bit name cldn igate reset or por value 0 0 0 0 0 0 0 0 these bits are applicable to all four ports. bit descriptions cldn: fault cool-down timer programming field. following a start, icut or ilim, a port shuts down, and the cool-down timer counts down. until the timer counts down to 0, the port will not be allowed to be powered on if the port is in semi-auto or auto mode. if in manual mode, the port can be powered on immediately with a push- button command by writing to pwonn in the power enable register. the cool-down timer is cancelled by power- on reset, device reset or port reset (see reset register ). the field programming is: cldn[1:0] nominal cool-down timer period 0x 1 s 10 2 s 11 4 s igate: gate pull-up current bit. igate sets the gate pull-up current. igate nominal gate pullup current ( a) 0 50 1 25
82 tps23861 slusbx9e ? march 2014 ? revised march 2016 www.ti.com product folder links: tps23861 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated 7.5.34 port n detect resistance register 7.5.34.1 port 1 detect resistance register command = 60h with 2 data byte (lsbyte first, msbyte second), read only lsb: 60h bits d7 d6 d5 d4 d3 d2 d1 d0 bit name port 1 resistance[7:0] reset or por value 0 0 0 0 0 0 0 0 msb: 61h bits d7 d6 d5 d4 d3 d2 d1 d0 bit name rs1[1:0] port 1 resistance[13:8] reset or por value 0 0 0 0 0 0 0 0 7.5.34.1.1 port 2 detect resistance register command = 62h with 2 data byte (lsbyte first, msbyte second), read only lsb: 62h bits d7 d6 d5 d4 d3 d2 d1 d0 bit name port 2 resistance[7:0] reset or por value 0 0 0 0 0 0 0 0 msb: 63h bits d7 d6 d5 d4 d3 d2 d1 d0 bit name rs2[1:0] port 2 resistance[13:8] reset or por value 0 0 0 0 0 0 0 0 7.5.34.1.2 port 3 detect resistance register command = 64h with 2 data byte (lsbyte first, msbyte second), read only lsb: 64h bits d7 d6 d5 d4 d3 d2 d1 d0 bit name port 3 resistance[7:0] reset or por value 0 0 0 0 0 0 0 0 msb: 65h bits d7 d6 d5 d4 d3 d2 d1 d0 bit name rs3[1:0] port 3 resistance[13:8] reset or por value 0 0 0 0 0 0 0 0
83 tps23861 www.ti.com slusbx9e ? march 2014 ? revised march 2016 product folder links: tps23861 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated 7.5.34.1.3 port 4 detect resistance register command = 66h with 2 data byte (lsbyte first, msbyte second), read only lsb: 66h bits d7 d6 d5 d4 d3 d2 d1 d0 bit name port 4 resistance[7:0] reset or por value 0 0 0 0 0 0 0 0 msb: 67h bits d7 d6 d5 d4 d3 d2 d1 d0 bit name rs4[1:0] port 4 resistance[13:8] reset or por value 0 0 0 0 0 0 0 0 bit descriptions most recent 2 point detection resistance measurement. the resistance value shown is usable only if rsn[1:0] are at 00 or 01. the i 2 c data transmission is a 2 byte transfer. port n resistance[13:0]: 14-bit data conversion result of detection resistance for port n. the equation defining the resistance measured is: where ? r = detection resistance, ? n = 14-bit value in port n resistance register ? r step = lsb value (6) useable resistance range lsb value 500 to 55 k 11.0966 rsn[1:0]: most recent detection result status on port n. if the state is 00, the 14-bit resistance value is calculated with a bit weight of 11.0966 /bit. if the state is 01, two additional detection fingers have been performed at higher detection currents (270 a and 540 a) in order to better measure the lower port impedance. the 14-bit resistance value is calculated with a bit weight of 4.625 /bit in this case. the detection result is maintained in the register in any operating mode following the detection. r sn1 r sn0 detect status r step bit weight 0 0 other 11.0966 /bit 0 1 low ( < 2 k ) additional detect 4.625 /bit 1 0 open circuit n/a 1 1 mosfet short fault n/a step r n r u
84 tps23861 slusbx9e ? march 2014 ? revised march 2016 www.ti.com product folder links: tps23861 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated 7.5.35 port n detect voltage difference register 7.5.35.1 port 1 detect voltage difference register command = 68h with 2 data byte (lsbyte first, msbyte second), read only lsb: 68h bits d7 d6 d5 d4 d3 d2 d1 d0 bit name port 1 voltage difference [7:0] reset or por value 0 0 0 0 0 0 0 0 msb: 69h bits d7 d6 d5 d4 d3 d2 d1 d0 bit name vds1[3:0] port 1 voltage difference [11:8] reset or por value 0 0 0 0 0 0 0 0 7.5.35.2 port 2 detect voltage difference register command = 6ah with 2 data byte (lsbyte first, msbyte second), read only lsb: 6ah bits d7 d6 d5 d4 d3 d2 d1 d0 bit name port 2 voltage difference [7:0] reset or por value 0 0 0 0 0 0 0 0 msb: 6bh bits d7 d6 d5 d4 d3 d2 d1 d0 bit name vds2[3:0] port 2 voltage difference [11:8] reset or por value 0 0 0 0 0 0 0 0 7.5.35.3 port 3 detect voltage difference register command = 6ch with 2 data byte (lsbyte first, msbyte second), read only lsb: 6ch bits d7 d6 d5 d4 d3 d2 d1 d0 bit name port 3 voltage difference [7:0] reset or por value 0 0 0 0 0 0 0 0 msb: 6dh bits d7 d6 d5 d4 d3 d2 d1 d0 bit name vds3[3:0] port 3 voltage difference [11:8] reset or por value 0 0 0 0 0 0 0 0
85 tps23861 www.ti.com slusbx9e ? march 2014 ? revised march 2016 product folder links: tps23861 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated 7.5.35.4 port 4 detect voltage difference register command = 6eh with 2 data byte (lsbyte first, msbyte second), read lsb: 6eh bits d7 d6 d5 d4 d3 d2 d1 d0 bit name port 4 voltage difference [7:0] reset or por value 0 0 0 0 0 0 0 0 msb: 6fh bits d7 d6 d5 d4 d3 d2 d1 d0 bit name vds4[3:0] port 4 voltage difference [11:8] reset or por value 0 0 0 0 0 0 0 0 this register is used to determine the presence of a legacy pd by measuring the pd input capacitance on the pi. a charge is injected into the pi, and the resulting v is reported. the v value shown is useable only if vdsn[3:0] = 0001. the i 2 c data transmission is a 2-byte transfer. bit descriptions port n voltage difference[11:0]: 12-bit data conversion result of the difference in voltage on the port as a result of a fixed charge injected into the port. the equation defining the resistance measured is: where ? c = port capacitance, f ? k = 81 x 10-6 coulomb ? n = 12-bit value in port n detect voltage difference register ? v step = lsb value (7) note the expression for port capacitance ignores the effect of any conductance in parallel with the capacitance being measured. the effect of parallel conductance is to give a higher value than the actual value of any capacitance present. useable capacitance range voltage difference lsb value 10 to 100 f 4.884 mv step k c n v # u
86 tps23861 slusbx9e ? march 2014 ? revised march 2016 www.ti.com product folder links: tps23861 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated vdsn[3:0]: most recent detect voltage difference result status on port n. if ? 0001 ? state, the 12-bit v value is useable. this measurement is made on a port if legacy detect is enabled using the legacy detect mode register. vdsn is set to the power-on reset state (0000b) when legacy detection is enabled until a v measurement is made. the detection result is maintained in the register in any operating mode following the measurement. the selection is as following: vdsn[3:0] voltage-difference measurement status 0000 power-on reset 0001 valid measurement 0010 unable to discharge pd input capacitance to 2.4 v before timeout 0011 unable to achieve 0.4v to take first measurement before timeout 0100 first measurement exceeds vdet-clamp (min) 0101 second measurement exceeds vdet-clamp (min) 0110 v < 0.5 v (insufficient signal) 7.5.36 reserved registers ? register 0x1b ? register 0x1d ? register 0x1e ? register 0x1f ? register 0x22 ? register 0x23 ? register 0x24 ? register 0x25 ? register 0x59 reserved: these registers are reserved for manufacturing or future use. undesirable behavior may result if these registers are written to.
87 tps23861 www.ti.com slusbx9e ? march 2014 ? revised march 2016 product folder links: tps23861 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated 8 application and implementation note information in the following applications sections is not part of the ti component specification, and ti does not warrant its accuracy or completeness. ti ? s customers are responsible for determining suitability of components for their purposes. customers should validate and test their design implementation to confirm system functionality. 8.1 introduction to poe power-over-ethernet (poe) is a means of distributing power to ethernet devices over the ethernet cable using either data or spare pairs. poe eliminates the need for power supplies at the ethernet device. common applications of poe are security cameras, ip phones and pda chargers. the host or mid-span equipment that supplies power is the power source equipment (pse). the load at the ethernet connector is the powered device (pd). poe protocol between pse and pd controlling power to the load is specified by ieee std 802.3at-2009. transformers are used at ethernet host ports, mid-spans and hubs, to interface data to the cable. a dc voltage can be applied to the center tap of the transformer with no effect on the data signals. as in any power transmission line, a relatively high 48 v is used to keep current low, minimize the effect of ir drops in the line and preserve power to the load. standard poe delivers approximately 13 w to a type 1 pd, and 25.5 w to a type 2 pd. figure 46 shows the overview schematic of a poe port. 8.2 application information the tps23861 is a four port, ieee 802.3at poe pse controller and can be used in very simple, low port count, automatic or high port count micro-controller managed applications. subsequent sections describe detailed design procedures for applications with different requirements including host control. figure 46. automatic 4-port operation schematic 14 13 12 11 10 9 8 7 6 5 4 3 2 1 vdd scl sdai sdao dgnd sen3 drain3 gate3 ksensb sen4 drain4 gate4 15 16 17 18 19 20 21 22 23 24 25 26 27 28 vpwr n/c aout ain shtdwn a3 agnd gate2 drain2 sen2 ksensa gate1 drain1 sen1 reset int 22.1 : : 0.1 p f 50v 0.1 p f 100v : : : 22.1 : 22.1 : 22.1 : smbj58a-13-f 0.1 p f 100v fdmc3612 : 10mq100ntrpbf c1s 1.5 vpwr p2 + - rj45 & xfmr smbj58a-13-f 0.1 p f 100v fdmc3612 : 10mq100ntrpbf c1s 1.5 vpwr p1 + - rj45 & xfmr (optional) (optional) TPS23861PW smbj58a-13-f 0.1 p f 100v fdmc3612 : 10mq100ntrpbf c1s 1.5 vpwr p3 + - rj45 & xfmr smbj58a-13-f 0.1 p f 100v fdmc3612 : 10mq100ntrpbf c1s 1.5 vpwr p4 + - rj45 & xfmr (optional) (optional) vpwr vdd
88 tps23861 slusbx9e ? march 2014 ? revised march 2016 www.ti.com product folder links: tps23861 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated application information (continued) the schematic of figure 46 depicts automatic mode operation of the tps23861, providing turnkey functionality ready to power poe loads. no connection to the i 2 c bus or any type of host control is required. in figure 46 the tps23861 automatically: 1. performs load detection. 2. performs classification including type-2 (two-finger) of up to class 4 loads. 3. enables power with protective foldback current limiting, and icut value based on load class. 4. shuts down in the event of fault loads and shorts. 5. performs maintain power signature function to ensure removal of power if load is disconnected. 6. undervoltage lock out occurs if vpwr falls below v puv_f (typical 26.5 v). following a power-off command, disconnect or shutdown due to a start, icut or ilim fault, the port powers down. following port power off due to a power off command or disconnect, the tps23861 continues automatic operation starting with a detection cycle. if the shutdown is due to a start, icut or ilim fault, the tps23861 enters into a cool-down period. after the end of the cool-down period the tps23861 continues automatic operation starting with a detection cycle. the tps23861 will not automatically apply power to a port under the following circumstances: ? the detect status is not resistance valid. ? if the classification status is overcurrent, class mismatch, or unknown. 8.2.1 kelvin current sensing resistor load current in each pse port is sensed as the voltage across a low-end current-sense resistor with a value of 255 m . for more accurate current sensing, kelvin sensing of the low end of the current-sense resistor is provided through pins ksensa for ports 1 and 2, and ksensb for ports 3 and 4. 8.2.2 connections on unused ports the tps23861 can be used on applications needing only 1 to 4 ports. on unused ports ground the senx pin and leave the gatex pin floating. drainx pins can be grounded or left open (leaving open may slightly reduce power consumption). one example of an unused port4 is shown in figure 47 . for detailed design and component selection information, see system examples . this schematic shows connections for an unused port4. figure 47. unused port4 connections ksensb sen4 drain4 gate4 ksensa gate1 drain1 sen1 15 16 17 18 14 13 12 11 22 : 255 m 250 m 47 : port 4 not used
89 tps23861 www.ti.com slusbx9e ? march 2014 ? revised march 2016 product folder links: tps23861 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated 8.3 typical application typical applications are shown for several port counts. the tps23861 is an effective choice for port counts less than the 4 ports provided, and these applications clearly show the connections for unused ports. applications are shown for both auto mode as well as semi-auto mode. operation in any mode except auto mode require i 2 c host support. the tps23861 provides useful telemetry in multi port applications to aid in implementing port power management. 8.3.1 two port, auto mode application with external port reset figure 48. two port auto mode application with port reset 8.3.1.1 design requirements table 12. design parameters design parameter value operating mode auto mode number/type of ports two type 2 ports other requirements push button port reset 14 13 12 11 10 9 8 7 6 5 4 3 2 1 vdd scl sdai sdao dgnd sen3 drain3 gate3 ksensb sen4 drain4 gate4 15 16 17 18 19 20 21 22 23 24 25 26 27 28 vpwr n/c aout ain shtdwn a3 agnd gate2 drain2 sen2 ksensa gate1 drain1 sen1 reset int r sen2 c vdd c vpwr r drn1 r drn2 r sen1 d p2a c p2 q p2 r s2a r s2b d p2b f p2 vpwr p2 + - rj45 & xfmr d p1a c p1 q p1 r s1a r s1b d p1b f p1 vpwr p1 + - rj45 & xfmr (optional) (optional) TPS23861PW r rst port reset vpwr vdd
90 tps23861 slusbx9e ? march 2014 ? revised march 2016 www.ti.com product folder links: tps23861 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated 8.3.2 four port, auto mode application figure 49. four port auto mode application 8.3.2.1 design requirements the design for the four port auto mode application is the same as for the two port design scaled up by two. in addition, the four port application does not require port reset so the reset pin may be connected directly to vdd. table 13. design parameters design parameter value operating mode auto mode number/type of ports four type 2 ports 14 13 12 11 10 9 8 7 6 5 4 3 2 1 vdd scl sdai sdao dgnd sen3 drain3 gate3 ksensb sen4 drain4 gate4 15 16 17 18 19 20 21 22 23 24 25 26 27 28 vpwr n/c aout ain shtdwn a3 agnd gate2 drain2 sen2 ksensa gate1 drain1 sen1 reset int r sen2 r drn3 c vdd c vpwr r drn4 r drn1 r drn2 r sen1 r sen3 r sen4 d p2a c p2 q p2 r s2a r s2b d p2b f p2 vpwr p2 + - rj45 & xfmr d p1a c p1 q p1 r s1a r s1b d p1b f p1 vpwr p1 + - rj45 & xfmr (optional) (optional) TPS23861PW d p3a c p3 q p3 r s3a r s3b d p3b f p3 vpwr p3 + - rj45 & xfmr d p4a c p4 q p4 r s4a r s4b d p4b f p4 vpwr p4 + - rj45 & xfmr (optional) (optional) vpwr vdd
91 tps23861 www.ti.com slusbx9e ? march 2014 ? revised march 2016 product folder links: tps23861 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated 8.3.3 eight port, semi-auto mode application using msp430 micro-controller figure 50. eight port semi-auto mode application 14 13 12 11 10 9 8 7 6 5 4 3 2 1 vdd scl sdai sdao dgnd sen3 drain3 gate3 ksensb sen4 drain4 gate4 15 16 17 18 19 20 21 22 23 24 25 26 27 28 vpwr n/c aout ain shtdwn a3 agnd gate2 drain2 sen2 ksensa gate1 drain1 sen1 reset int r sen2 r drn3 c vdd c vpwr r drn4 r drn1 r drn2 r sen1 r sen3 r sen4 d p2a c p2 q p2 r s2a r s2b d p2b f p2 vpwr p2 + - rj45 & xfmr d p1a c p1 q p1 r s1a r s1b d p1b f p1 vpwr p1 + - rj45 & xfmr (optional) (optional) TPS23861PW d p3a c p3 q p3 r s3a r s3b d p3b f p3 vpwr p3 + - rj45 & xfmr d p4a c p4 q p4 r s4a r s4b d p4b f p4 vpwr p4 + - rj45 & xfmr (optional) (optional) vpwr vdd 14 13 12 11 10 9 8 7 6 5 4 3 2 1 vdd scl sdai sdao dgnd sen3 drain3 gate3 ksensb sen4 drain4 gate4 15 16 17 18 19 20 21 22 23 24 25 26 27 28 vpwr n/c aout ain shtdwn a3 agnd gate2 drain2 sen2 ksensa gate1 drain1 sen1 reset int r sen6 r drn7 c vdd c vpwr r drn8 r drn5 r drn6 r sen5 r sen7 r sen8 d p6a c p6 q p6 r s6a r s6b d p6b f p6 vpwr p6 + - rj45 & xfmr d p5a c p5 q p5 r s5a r s5b d p5b f p5 vpwr p5 + - rj45 & xfmr (optional) (optional) TPS23861PW d p7a c p7 q p7 r s7a r s7b d p7b f p7 vpwr p7 + - rj45 & xfmr d p8a c p8 q p8 r s8a r s8b d p8b f p8 vpwr p8 + - rj45 & xfmr (optional) (optional) vpwr vdd addr=0x28 addr=0x20 i2c host device r scl r sda vdd
92 tps23861 slusbx9e ? march 2014 ? revised march 2016 www.ti.com product folder links: tps23861 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated 8.3.3.1 design requirements the design for the eight port semi-auto mode application is the same as for the two port design scaled up by four. in addition, the eight port application does not require port reset so the reset pin may be connected directly to vdd. two tps23861 devices are used in the eight port configuration and are managed by the i 2 c host device. the factory default i 2 c address for each tps23861 is 0x20 when the a3 pin is low and 0x28 when the a3 pin is left open or tied to vdd. table 14. design parameters design parameter value operating mode semi-auto mode number/type of ports eight type 2 ports other requirements micro-controller managed 8.3.4 detailed design procedure 8.3.4.1 power pin bypass capacitors ? c vpwr : 0.1 f, 100 v, x7r ceramic at pin 28 (vpwr) ? c vdd : 0.1 f, 50 v, x7r ceramic at pin 1 (vdd) 8.3.4.2 per port components ? r drnn : r drnn should be a 47- , 5%, 0.1-w resistor in an 0603 smt package. ? r senn : r senn should be a 22.1- , 1%, 0.1-w resistor in an 0603 smt package. ? c pn : 0.1- f, 100-v, x7r ceramic between vpwr and pn- ? r sna / r snb : the port current sense resistors can be either a combination of two 0.51- , 1% resistors in parallel (0.255 ) or four 1.00- , 1% resistors in parallel (0.250 ). the most common usage employs dual 0.51- , 1%, 0.25-w resistors in an 0805 smt package. power dissipation for the resistor pair at maximum i cut is approximately 117 mw (~58 mw each). ? q pn : the port mosfet can be a small, inexpensive device with average performance characteristics. ? bvdss should be 100 v minimum for high voltage surge environment considerations. ? r ds(on) (v gs = 10 v) should be between 50 m and 150 m for power dissipation considerations. ? the power dissipation for q pn with r ds(on) = 100 m at maximum i cut is approximately 46 mw. ? input capacitance (c iss ) should be less than 2000 pf. ? gate charge (q g ) at v gaten = 12.5 v should be less than 50 nc (see note below). note for applications requiring faster response times under soft overload conditions (1 to 1.5 x ilim), q g @ v gaten = 12.5 v may be required to be < < 50 nc. ? f pn : the port fuse should be a slow blow type rated for at least 60 vdc and above ~2 x i cut(max) . the cold resistance should be below 200 m to reduce the dc losses. the power dissipation for f pn with a cold resistance of 180 m at maximum i cut is approximately 83 mw. ? d pna : the port tvs should be rated for the expected port surge environment. d pna should have a minimum reverse standoff voltage of 58 v and a maximum clamping voltage of 95 v at the expected peak surge current. ? d pnb : the negative clamp diode is optional for extreme surge environments. d pnb should be rated for v r = 100 v minimum and be able to survive the expected surge current. low forward voltage drop at the rated current is beneficial.
93 tps23861 www.ti.com slusbx9e ? march 2014 ? revised march 2016 product folder links: tps23861 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated 8.3.4.3 system level components (not shown in the schematic diagrams) ? tvs: the system tvs should have a minimum reverse standoff voltage of 58 v and a maximum clamping voltage of 95 v at the expected peak-surge current. ? bulk capacitor: the system bulk capacitor(s) should be rated for 100 v and can be an aluminum electrolytic type. lower values can be paralleled to achieve at least 47 f per four ports. ? digital i/o pull-up resistors: reset, ain, a3, and shtdwn are internally pulled up to vdd with a 50-k (typical) resistor. a stronger pull-up resistor can be added externally such as a 10 k , 1%, 0.063 w type in a smt package. scl, sdai, sdao, and int require external pull-up resistors within a range of 1 k to 10 k depending on the total number of devices on the bus. the aout pin is either connected to an upstream device (to the ain pin) or left unconnected and as such requires no external pull-up resistor. ? ethernet data transformer (per port): the ethernet data transformer must be rated to operate within the ieee802.3at standard in the presence of the dc port current conditions. the transformer is also chosen to be compatible with the ethernet phy. the transformer may also be integrated into the rj45 connector and cable terminations. ? rj45 connector (per port): the majority of the rj45 connector requirements are mechanical in nature and include tab orientation, housing type (shielded or unshielded), or highly integrated. an integrated rj45 consists of the ethernet data transformer and cable terminations at a minimum. the integrated type may also contain the port tvs and common mode emi filtering. ? cable terminations (per port): the cable terminations typically consist of series resistor (usually 75 ) and capacitor (usually 10 nf) circuits from each data transformer center tap to a common node which is then bypassed to a chassis ground (or system earth ground) with a high-voltage capacitor (usually 1000 pf to 4700 pf at 2 kv).
94 tps23861 slusbx9e ? march 2014 ? revised march 2016 www.ti.com product folder links: tps23861 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated 8.3.5 application curves figure 51. figure 52. figure 53. figure 54. figure 55. figure 56. inrush current load current pd detected (four point) one-event class (class 0 current) pd detected (four point) one-event class (class 3 current) searching for pd searching for pd pd detected pd classified cls1 mrk1 cls2 mrk2 two-event class (class 4 current)
95 tps23861 www.ti.com slusbx9e ? march 2014 ? revised march 2016 product folder links: tps23861 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated 8.4 system examples 8.4.1 overcurrent and overload protection the tps23861 provides three levels of overcurrent protection. during the t start period immediately following power up, inrush current protection is provided as described in inrush protection . this protection allows the input capacitance of the pd to charge to the full input voltage on the power interface while ensuring the pass fet remains within its safe operating area. following the end of the t start period a two-tiered current-limit protection scheme is applied to the ports. the first level (i.e., lower current) is the icut current limit. the icut current-limit threshold is set using the icutnm config registers and includes a timeout, t ovld , set using ticut field in the timing configuration register. when the ticut timer times out because the icut current threshold is exceeded, the port is powered off, and the icutn bit in the fault event register is set with the option of asserting an interrupt. this delay in powering down the port provides protection against spurious power downs during moderate load transients. see icut current limit . the second level of powered-on current-limiting protection is the ilim current limit. the ilim current limit is a hard limit . that is, hardware protection including voltage foldback is imposed when the ilim current threshold is reached. this second level of protection is invoked in the event of extreme overload or short circuit. the ilim current-limit value is set using the poepn bits in the poe plus register. also, when the ilim value is reached, the ilim timer is started. when the ilim timer times out, the port is powered off and the ilimn bit in the start/ilim event register is set with the option of asserting an interrupt. see foldback protection (ilim) . 8.4.2 inrush protection inrush-current limiting is provided by the tps23861 according to the curve in figure 57 . when the port is first powered on, the tstart timer is started. while the tstart timer is counting, the port current is limited to i inrush , as shown in figure 57 . if at the end of t start period the current is still limiting at i inrush , the port is powered off and the strtn bit in the start/ilim event register is set with the option of asserting an interrupt. figure 57. foldback during inrush (at port turn on) i inrush vs v port 0 50 100 150 200 250 300 350 400 450 500 0 10 20 30 40 50 60 70 current limit - ma port voltage -v c002
96 tps23861 slusbx9e ? march 2014 ? revised march 2016 www.ti.com product folder links: tps23861 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated system examples (continued) (1) poepn bit should be set according to icut value for host to ensure the icut and ilim relationship. 8.4.3 icut current limit in addition to the absolute current limit imposed by the ilim foldback curve ( figure 58 ) the tps23861 supports an additional level of current-limit protection. when the icut current-limit threshold is reached, the ticut timer starts counting down. when it reaches zero the port is powered down. if the port current drops below the icut current-limit threshold while the ticut timer is counting, the ticut timer counts up, albeit at a slower rate, without exceeding the maximum count corresponding to the setting in the ticut field. the icut current-limit threshold is meant to be applied such that its setting is below the setting of the ilim current limit. that is, the icut threshold should be reached before the tps23861 asserts foldback control over the port current via an ilim current limit. to this end, the icut threshold should be set lower than the ilim current limit. this must be accomplished by the host except when in auto mode (or the auto bit is set). in that case, the settings for icut and ilim is properly set based on classification results before the port is powered on. the icut current limit threshold (icut) is programmable on a per-port basis in the 3-bit icut port n fields in the icutnm config registers. the encoding of the icut port n fields is shown in table 15 . the current values in table 15 are nominal values. table 15. icut current limit encoding icut port n field icut (ma) poepn (1) 000 374 0 001 110 0 010 204 0 011 374 0 100 754 1 101 592 1 110 645 1 111 920 1
97 tps23861 www.ti.com slusbx9e ? march 2014 ? revised march 2016 product folder links: tps23861 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated 8.4.4 foldback protection (ilim) the tps23861 features two types of foldback protection mechanisms for complete mosfet protection. during inrush at port power on, the foldback is based on the port voltage as shown in figure . note the inrush-current profile remains the same no matter what the state is of the poepn bit in the poe plus register. after the port has been powered on and power good is valid, a dual-slope foldback current limit is applied, providing protection against partial and total short-circuit at port output, while still being able to maintain the port powered during normal transients in the tps23861 input voltage or load current. refer to figure 58 . note that setting the poepn bit selects the 2x curve while clearing it selects the 1x curve. the tlim timer starts counting down when the current-limit threshold in figure 57 and figure 58 is reached. when it reaches zero the port is powered down. if the ilim current-limit condition is cleared while the tlim timer is counting, the tlim timer counts up, at a slower rate, without exceeding the maximum count corresponding to the setting in the tlim field which is located in the timing configuration register. if the port experiences a short circuit, the tps23861 forces zero volts on the gate of the external fet to protect it from destruction. within microseconds the foldback circuit engages, and until the ilim timeout is reached, the port current is controlled according to the foldback schedule. the ilim current limit is to be applied such that its setting is greater than the setting of the icut current threshold. that is, an icut current-limit condition should occur before the tps23861 asserts foldback control over the port current via an ilim current limit. to this end, the ilim current limit must be set greater than the icut current threshold. this must be accomplished by the host except when in auto mode (or the auto bit is set). in that case, the settings for icut and ilim will be properly set based on classification results before the port is powered on. figure 58. foldback port on (ilim vs v drain ) 0 200 400 600 800 1000 1200 0 10 20 30 40 50 60 current limit - ma mosfet drain voltage -v c003
98 tps23861 slusbx9e ? march 2014 ? revised march 2016 www.ti.com product folder links: tps23861 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated 8.4.5 kelvin current sensing resistor load current in each pse port is sensed as the voltage across a low-end current-sense resistor with a value of 255 m . alternatively, a 250-m resistor may be used. if a 250-m sense resistor is used the m250 bit in the general mask 1 register must be set. for more accurate current sensing, kelvin sensing of the low end of the current-sense resistor is provided through pins ksensa for ports 1 and 2, and ksensb for ports 3 and 4. figure 59 illustrates the kelvin-sensing scheme. figure 59. kelvin current-sense connection scl agnd dgnd ksensx int sdao drainn gaten vdd vpwr senn 22 100 nf 100 v 47 255 m / 250 m : note: only port n shown tps23861 portn 48 v 3.3 v sdai
99 tps23861 www.ti.com slusbx9e ? march 2014 ? revised march 2016 product folder links: tps23861 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated 9 power supply recommendations 9.1 vdd the recommended vdd supply voltage requirement is 3.3 v, 0.3 v. each tps23861 requires approximately 5 ma typical and 6 ma maximum from the vdd supply. the vdd supply can be generated from vpwr with a linear regulator (tps7a4001) for single tps23861/auto mode based pse or a buck-type regulator (lm5007 or lm5019 based) for a higher port count pse using multiple tps23861 devices operating in auto or semi-auto modes. the power supply design must ensure the vdd rail rises monotonically through v uvddr without any droop below v uvddf as the loads are turned on. this is accomplished with proper bulk capacitance across the vdd rail for the expected load current steps over worst case design corners. furthermore, the combination of decoupling capacitance and bulk storage capacitance must hold the vdd rail above the uvlo_fall threshold during any expected transient outages once power is applied. 9.2 vpwr the recommended vpwr supply voltage requirement is 44 v to 57 v. a power supply with a nominal 48-v or 54-v output can support both type 1 and type 2 pd requirements. the output current required from the vpwr supply depends on the number and type of ports required in the system. the tps23861 can be configured for type 1 and type 2 ports and the current limit is set proportionally. icut for a type 1 port is 374 ma , 5%, and for a type 2 port is 645 ma, 5%. size the vpwr supply accordingly for the number and type of ports to be supported. as an example, the vpwr power supply rating should be greater than 3.2 a for eight type 1 ports or greater than 5.5 a for eight type 2 ports, assuming maximum port and standby currents. 9.3 vpwr-reset sequencing the voltage on the reset pin (v reset ) should be kept below 0.9 v until v vpwr exceeds v uvlopw_r . if vdd is turned on after v vpwr exceeds v uvlopw_r then no delay for reset is required. if vdd is on before v vpwr exceeds v uvlopw_r then a delay for reset is required. this delay can be provided by the system host or with a capacitor (c rst ) connected to the reset pin using the internal (50 k typical) or external pullup resistor. note for the schematic diagrams shown in figure 36 , figure 46 , figure 48 , figure 49 , and figure 50 , the vdd power supply is turned on after the vpwr power supply exceeds v uvlopw_r . more detail regarding tps23861 power-on sequencing can be obtained by referring to the application note, tps23861 power-on considerations, slva723 .
100 tps23861 slusbx9e ? march 2014 ? revised march 2016 www.ti.com product folder links: tps23861 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated 10 layout 10.1 layout guidelines 10.1.1 port current kelvin sensing ksensa is shared between sen1 and sen2, while ksensb is shared between sen3 and sen4. in order to optimize the accuracy of the measurement, the pcb layout must be done carefully to minimize impact of pcb trace resistance. refer to figure 60 as an example. figure 60. kelvin sense layout example ksensa route to tps23861 r s1a/b r s2a/b shape connecting r s1a/b and r s2a/b to ksensa vias connecting shape to gnd layer to r sen1 to r sen2
101 tps23861 www.ti.com slusbx9e ? march 2014 ? revised march 2016 product folder links: tps23861 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated 10.2 layout example figure 61. four port layout example 10.2.1 component placement and routing guidelines 10.2.1.1 power pin bypass capacitors c vpwr : place close to pin 28 (vpwr) and connect with low inductance traces and vias according to figure 61 . c vdd : place close to pin 1 (vdd) and connect with low inductance traces and vias according to figure 61 . 10.2.1.2 per-port components r sna / r snb : place according to figure 60 in a manner that facilitates a clean kelvin connection with ksensea/b. q pn : place q pn around the tps23861 as illustrated in figure 61 . provide sufficient copper from q pn-d to f pn . r drnn : place r drnn near to q pn-d . connect to drainn pins as illustrated in figure 61 . r senn : place r senn near to q pn-s . connect to senn pins as illustrated in figure 61 . f pn , c pn , d pna , d pnb : place this circuit group near the rj45 port connector (or port power interface if a daughter board type of interface is used as illustrated in figure 61 ). connect this circuit group to q pn-d / gnd (tps23861- agnd) using low inductance traces. top side bottom side (not mirrored) r drn1 r drn2 r drn4 r drn3 r sen1 r sen2 r sen4 r sen3 c vdd c vpwr r s3a r s3b r s4a r s4b r s1a r s1b r s2a r s2b q p1 q p2 q p4 q p3 TPS23861PW f p3 f p2 f p4 f p1 c p3 c p2 c p4 c p1 d p3a d p3b d p2b d p2a d p4a d p1a d p4b d p1b j io ksensb ksensa vpwr gnd gnd p3 p2 p4 p1
102 tps23861 slusbx9e ? march 2014 ? revised march 2016 www.ti.com product folder links: tps23861 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated 11 device and documentation support 11.1 documentation support 11.1.1 related documentation ic package thermal metrics application report, spra953 . 11.2 community resources the following links connect to ti community resources. linked contents are provided "as is" by the respective contributors. they do not constitute ti specifications and do not necessarily reflect ti's views; see ti's terms of use . ti e2e ? online community ti's engineer-to-engineer (e2e) community. created to foster collaboration among engineers. at e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. design support ti's design support quickly find helpful e2e forums along with design support tools and contact information for technical support. 11.3 trademarks e2e is a trademark of texas instruments. all other trademarks are the property of their respective owners. 11.4 electrostatic discharge caution these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. 11.5 glossary slyz022 ? ti glossary . this glossary lists and explains terms, acronyms, and definitions.
103 tps23861 www.ti.com slusbx9e ? march 2014 ? revised march 2016 product folder links: tps23861 submit documentation feedback copyright ? 2014 ? 2016, texas instruments incorporated 12 mechanical, packaging, and orderable information the following pages include mechanical, packaging, and orderable information. this information is the most current data available for the designated devices. this data is subject to change without notice and revision of this document. for browser-based versions of this data sheet, refer to the left-hand navigation.
package option addendum www.ti.com 26-feb-2016 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples TPS23861PW active tssop pw 28 50 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 125 TPS23861PW TPS23861PWr active tssop pw 28 2000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 125 TPS23861PW (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release.
package option addendum www.ti.com 26-feb-2016 addendum-page 2 in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant TPS23861PWr tssop pw 28 2000 330.0 16.4 6.9 10.2 1.8 12.0 16.0 q1 package materials information www.ti.com 26-feb-2016 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) TPS23861PWr tssop pw 28 2000 367.0 367.0 38.0 package materials information www.ti.com 26-feb-2016 pack materials-page 2

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